A screening method and on-chip measurement system for integrated circuit aging reliability
An on-chip measurement and integrated circuit technology, which is applied in the direction of electronic circuit testing, measuring electronics, and measuring devices, can solve the problems of inability to achieve high-precision and fast prediction of the aging speed of integrated circuits, poor correlation between aging speed and critical path aging speed, and aging speed Low correlation and other issues, to achieve the effects of rapid aging reliability screening, occupying a small additional area, and easy integration
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[0081] Apply a kind of screening method and on-chip measurement system of integrated circuit aging reliability designed by the present invention to carry out emulation and test:
[0082]HSPICE 2014 software is used for testing, the test uses 28nm process library for simulation, and VCS is used for functional simulation of the test system. Use the Monte Carlo simulation method in Hspice to verify the test accuracy of the test circuit under manufacturing uncertainty, adding 10% W, 10% L and 25% V to the test th manufacturing uncertainty. Where, W is the gate width, L is the gate length, V th is the threshold voltage of the MOS tube. The functional simulation waveform diagram of the on-chip measurement system can be found in Image 6 As shown, the on-chip measurement system can realize the delay measurement of the critical path in the normal operation of the circuit. When the power supply voltage of the on-chip measurement system is 1.05V, the average delay difference of a si...
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