Method for fabricating interconnection structure

Abstract

The present invention provides a method for fabricating an interconnection structure. The method comprises providing a semiconductor substrate; forming a trench in the semiconductor substrate; formingan interconnection layer to fill the trench and cover the semiconductor substrate; after self-annealing is performed for a period of time, removing a portion of the interconnection layer covering thesemiconductor substrate to form the interconnection structure; and forming a covering layer to cover the semiconductor substrate and the interconnection structure, wherein the period of time is in arange of 1h to 10h. Since the grain size on the semiconductor substrate has a self-annealing phenomenon at room temperature, the self-annealing is performed after the interconnection layer is formed,and then the interconnection layer is removed and the covering layer is formed after 1h to 10h. Though the self-annealing takes a longer time than the rapid annealing, the interconnection layer can achieve stress matching in the small-sized trench to avoid a peeling phenomenon, thereby avoiding the problem of semiconductor line disconnection and ensuring the yield of the semiconductor products.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing processes, and in particular, to a manufacturing method of an interconnect structure. Background technique [0002] As the size of semiconductor devices continues to decrease, the fabrication of interconnect structures also faces enormous challenges. Among them, interconnect refers to wires supported by conductive materials such as aluminum, polysilicon or copper that transmit electrical signals to different parts of the chip. Interconnects are also used as common metal connections between on-chip devices and the entire package. In addition to the problems of process uniformity and filling difficulties, small-sized metal connections / trenches also face the problem of disconnection caused by stress mismatch in the manufacturing process, which affects local stress, such as metal / dielectric properties, electroplating, etc. Liquid impurities, plating speed and annealing pr...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a method for manufacturing an interconnection structure to solve the problem of trench disconnection caused by the stress mismatch of the semiconductor substrate in the prior art

Images