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Apparatus and method for processing instructions

A technology for processing instructions and instructions, which is applied in the system field of combined division and multiplication-subtraction operations, can solve problems such as performance loss, achieve the effects of reducing execution time, obtaining operating efficiency, and reducing circuits

Pending Publication Date: 2019-04-09
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This results in a performance loss when the remainder is calculated by the hardware during the division process

Method used

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  • Apparatus and method for processing instructions
  • Apparatus and method for processing instructions
  • Apparatus and method for processing instructions

Examples

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Embodiment Construction

[0019] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The disclosed subject matter may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosed subject matter to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

[0020] It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. to, directly connected to, or coupled to, another element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as be...

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PUM

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Abstract

The invention discloses an apparatus and a method for processing instructions. The apparatus may include a decoder circuit, a scheduler circuit, and an execution circuit. The decoder circuit may be configured to detect, within an instruction stream, a first instruction followed by a second instruction, wherein the first instruction takes as input a dividend and a divisor, and wherein the second instruction produces a remainder. The scheduler circuit may be configured to: merge the first and second instructions into a third instruction, wherein the third instruction takes as input the dividendand the divisor, and produces the remainder, replace, within an instruction pipeline, the first instruction with the third instruction, and delete, within the instruction pipeline, the second instruction. The execution circuit may be configured to execute the third instruction.

Description

technical field [0001] The present disclosure relates to circuits, and more particularly, to systems and methods for incorporating divide and multiply-subtract operations. Background technique [0002] In computing, the modulo operation finds the remainder after dividing one number by another (sometimes called the modulus). In division, the dividend is divided by the divisor to get the quotient. The remainder is the amount "left over" after performing some calculations. [0003] Given two numbers, a (the dividend) and n (the divisor), modulo n (abbreviated "mod n") is the remainder of Euclidean division (a divided by n) of a and n. For example, the expression "5 mod 2" will equal 1 because dividing 5 by 2 gives a quotient of 2 and a remainder of 1, and "9 mod 3" will equal 0 because dividing 9 by 3 has a quotient of 3 and leaves a remainder of 0; After taking 3 three times, there is no number that can be subtracted from 9. [0004] Some instruction set architectures (ISA...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3867G06F9/3001G06F9/30181G06F7/52G06F7/50G06F9/3016
Inventor 阿迪亚·库马尔德普·古普塔邦尼·科利特·塞克斯顿
Owner SAMSUNG ELECTRONICS CO LTD
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