A multifunctional and efficient dynamic chip verification simulation method and device

Abstract

The invention discloses a method and device for efficient dynamic chip verification and simulation, which maintains a unified and configurable verification case management list, dynamically adjusts the number of verification case simulation executions through real-time interaction with a server cluster, and completes the dynamic parallel to the maximum extent. Simulation runs for large-scale verification use cases. After the regression is complete, perform a quadratic regression in debug mode for the regression result error case. This method makes full use of the server cluster hardware resources, dynamically adjusts the number of parallel execution verification cases in real time, improves the automation level of verification use case regression, reduces the workload of verification personnel, and shortens the research and development cycle of chip verification work. The efficiency improvement is even more significant.

Description

Technical field [0001] The invention generally involves chip verification simulation technology. More specific, the invention involves a multi -functional high -efficiency dynamic chip verification simulation method and equipment. Background technique [0002] With the increasing complexity of the chip itself and the pressure of project progress that has been existed, how to complete the chip verification work with quality and efficiently is a technical problem that verification personnel need to solve. When the chip design code is stable, the verification engineer design large -scale verification use cases to ensure that the function of the entire chip is correct. As the size of the chip continues to increase, the number of verification use cases has also increased significantly. As the verification work is carried out, design defects will be constantly found. This requires the designer to modify the current chip design, but the modification design may have incorrect modificatio...

AI Technical Summary

Problems solved by technology

With the development of the verification work, design defects will continue to be discovered, which requires designers to modify the current chip design, but modifying the design may cause incorrect modifications or other abnormal functions, so each code modification needs to be modified. Regression validation for all use cases

If this work is carried out artificially, it will be affected by factors such as working hours and manpower efficiency, and cannot be completed most efficiently

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