A multifunctional high-efficiency dynamic chip verification simulation method and device

Abstract

The invention discloses a multifunctional high-efficiency dynamic chip verification simulation method and device, which maintain a unified and configurable verification case management list, dynamically adjust the simulation execution quantity of verification cases through real-time interaction with a server cluster, and dynamically complete simulation operation of large-scale verification cases to the maximum extent in parallel. And after the regression is completed, secondary regression of the debugging mode is carried out on a regression result error use case. According to the method, hardware resources of the server cluster are fully utilized, the number of verification cases which are executed in parallel is dynamically adjusted in real time, the automation level of regression of theverification cases is improved, the workload of verification personnel is reduced, the research and development period of chip verification work is shortened, and the efficiency is more remarkably improved for the application condition of a multi-project shared server cluster.

Description

technical field [0001] The present invention generally relates to the technical field of chip verification simulation. More specifically, the present invention relates to a multifunctional and efficient dynamic chip verification simulation method and device. Background technique [0002] With the increasing complexity of the chip itself and the ever-existing project schedule pressure, how to complete the chip verification work with high quality and efficiency is a technical problem that verification personnel need to solve. When the chip design code is stable, verification engineers design large-scale verification use cases to ensure the correct function of the entire chip. As the chip size continues to increase, the number of verification use cases has also increased significantly. With the development of the verification work, design defects will continue to be discovered, which requires the designer to modify the current chip design, but the modification of the design m...

AI Technical Summary

Problems solved by technology

With the development of the verification work, design defects will continue to be discovered, which requires designers to modify the current chip design, but modifying the design may cause incorrect modifications or other abnormal functions, so each code modification needs to be modified. Regression validation for all use cases

If this work is carried out artificially, it will be affected by factors such as working hours and manpower efficiency, and cannot be completed most efficiently

Images