A sparse convolutional neural network accelerator and an implementation method

Abstract

The invention relates to a sparse convolutional neural network accelerator and a realization method, and the method comprises the steps: reading the connection weight of a sparse network in an off-chip DRAM into a weight input buffer area, decoding the connection weight through a weight decoding unit, and storing the connection weight in a weight on-chip global buffer area; Reading neurons into aneuron input buffer area, decoding the read neurons through a neuron decoding unit, and storing the decoded neurons in a neuron on-chip global buffer area; Determining a calculation mode of the PE calculation unit array according to the configuration parameters of the current layer of the neural network, and sending neurons and connection weights which are arranged after decoding to a PE calculation unit; Calculating the product of the neuron and the connection weight; In the accelerator, the multipliers in the PE units are all replaced by the shifters, and all basic modules can be configuredaccording to network calculation and hardware resources, so that the accelerator has the advantages of high speed, low power consumption, small resource occupation and high data utilization rate.

Description

technical field [0001] The invention belongs to the technical field of deep neural network acceleration computing, and relates to a sparse convolutional neural network accelerator and an implementation method. Background technique [0002] The superior performance of Deep Neural Network (DNN) comes from its ability to use statistical learning to obtain an efficient representation of the input space from large amounts of data and extract high-level features from raw data. However, these algorithms are computationally intensive. As the number of network layers continues to increase, DNN has higher and higher requirements for storage resources and computing resources, making it difficult to deploy on embedded devices with limited hardware resources and tight power budgets. DNN model compression technology is beneficial to reduce network model memory usage, reduce computational complexity and system power consumption, etc. On the one hand, it can improve the operating efficiency...

AI Technical Summary

Problems solved by technology

Most of the existing neural network model research focuses on improving the accuracy of network recognition. Even the lightweight network model ignores the computational complexity of hardware acceleration, and the floating-point data representation leads to excessive consumption of hardware resources.

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