High-maintaining-voltage NLDMOS and manufacturing method thereof

Abstract

The invention provides a high-maintaining-voltage NLDMOS, which comprises: a high-voltage P well, first and second N drift regions, a P-type blocking layer, N+ injection regions, a shallow trench isolation region and a gate, wherein the first and second N drift regions are arranged on both sides of the high-voltage P well; the P-type blocking layer is formed in the high-voltage P well and positioned between the first and second N drift regions; the N+ injection regions are formed in the first and second N drift regions respectively and serve as a source and a drain respectively; the shallow trench isolation region is arranged in a region, close to the source, of the second N drift region and is connected with the drain; and the gate is formed above a position between the source and the shallow trench isolation region. Through additionally arranging the P-type blocking layer with high concentration in the high-voltage P well under the gate of the NLDMOS by means of ion implantation, theconcentration of a base region of a transverse parasitic NPN triode at a shallow portion of the substrate is increased by means of the P-type blocking layer, and the current gain of the transverse parasitic NPN triode is decreased, thereby decreasing the current gain of a parasitic NPN of the NLDMOS, suppressing the strong hysteresis effect of the high-voltage NLDMOS, and increasing the maintaining voltage of the high-voltage NLDMOS.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a high sustain voltage NLDMOS and a manufacturing method thereof. Background technique [0002] The anti-static protection design of high-voltage circuits has always been a technical problem, because the core of high-voltage circuits: high-voltage devices (such as LDMOS) are not suitable for anti-static protection design like ordinary low-voltage devices, and high-voltage devices are often due to their own device structure. However, it exhibits strong hysteresis effect characteristics, that is, when the hysteresis effect occurs, the maintenance voltage is much lower than the trigger voltage, or even far lower than the working voltage, which is easy to trigger the latch-up effect. figure 1 It is the hysteresis effect curve diagram of the high-voltage process platform 43VNLDMOS in the prior art, such as figure 1 As shown, the trigger voltage of the high-...

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Problems solved by technology

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a high sustain voltage NLDMOS and its manufacturing method, which is used to solve the problem of too low sustain voltage caused by the strong hysteresis effect of the high-voltage NLDMOS in the prior art

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