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An integrated radiation-resistant high-voltage soi device and its manufacturing method

A manufacturing method and anti-radiation technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., to achieve the effects of increasing concentration, improving anti-single event latch-up ability, and reducing parallel resistance

Active Publication Date: 2022-08-02
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The object of the present invention is to provide an integrated radiation-resistant high-voltage SOI device and its manufacturing method to solve the problem of ESD devices in the radiation-resistant high-voltage CMOS process proposed in the background art

Method used

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  • An integrated radiation-resistant high-voltage soi device and its manufacturing method
  • An integrated radiation-resistant high-voltage soi device and its manufacturing method
  • An integrated radiation-resistant high-voltage soi device and its manufacturing method

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Embodiment 1

[0040] The invention provides an integrated radiation-resistant high-voltage SOI device, the structure of which is as follows figure 1 As shown, it includes a P-type substrate 11, a buried oxide layer 21, and an N-type epitaxial layer 13 formed in sequence; the surface of the N-type epitaxial layer 13 is provided with a high-voltage NMOS device 71, a high-voltage PMOS device 72, and a high-voltage ESD device 73; The integrated radiation-resistant high-voltage SOI device further includes an isolation oxide layer 22, a gate oxide layer 23, a pre-metal dielectric layer 24, a first P-type doped region 41, a second P-type doped region 42, and a third P-type doped region. 43. Fourth P-type doping region 44, fifth P-type doping region 45, first N-type doping region 31, second N-type doping region 32, polysilicon 51, polycrystalline gate electrode 52, source metal Electrode 61, drain metal electrode 62, anode metal electrode 63, cathode metal electrode 64; the first N-type doping regi...

Embodiment 2

[0042] The invention also provides a manufacturing method of an integrated radiation-resistant high-voltage SOI device, which is fabricated on a silicon-on-insulator material, such as figure 2 As shown, the silicon-on-insulator has a P-type substrate 11, a buried oxide layer 21 and a top layer of silicon 12 stacked sequentially from bottom to top, including the following steps:

[0043] like image 3 As shown, an ion implantation process is used to implant P-type impurities on the top layer silicon 12 to form a first P-type doped region 41; the implantation dose of the first P-type doped region 41 is 1E13-1E15 cm -2 ;

[0044] like Figure 4 As shown, an N-type epitaxial layer 13 is formed on the buried oxide layer 21 by an epitaxial process; the N-type epitaxial layer 13 covers the first P-type doped region 41 ;

[0045] like Figure 5 As shown, the deep silicon trench is etched on the N-type epitaxial layer 13 by photolithography and etching process, and the isolation o...

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Abstract

The invention discloses an integrated radiation-resistant high-voltage SOI device and a manufacturing method thereof, belonging to the field of semiconductors. A third P-type doped region is simultaneously formed in the high-voltage PMOS device and the high-voltage ESD device. The trigger voltage of the high-voltage ESD device is determined by the junction breakdown of the third P-type doped region and the N-type epitaxial layer. According to the operating voltage of the circuit, This junction breakdown design can be done. In the integrated high-voltage ESD device, a third P-type doped region is introduced on the surface of the second P-type doped region, which increases the base region concentration of the parasitic triode NPN device, reduces the base region transport coefficient, and avoids single particle radiation. The high-voltage ESD device is turned on earlier, thereby improving the device's resistance to single-event latch-up, while also increasing the device's sustain voltage. The first P-type doped region above the buried oxide layer reduces the parallel resistance of the emitter junction of the parasitic NPN triode, improves the turn-on threshold of the parasitic NPN triode, and further improves the anti-single event latch-up capability of the ESD device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an integrated radiation-resistant high-voltage SOI device and a manufacturing method thereof. Background technique [0002] The phenomenon of electrostatic discharge widely exists in nature, and it is one of the important reasons for the failure of integrated circuit products. Integrated circuit products are easily affected by electrostatic discharge during their manufacturing and assembly processes, resulting in reduced product reliability or even damage. Electro-Static Discharge (ESD device) design is an important part of integrated circuit reliability design, and with the development of integrated circuit technology, more challenges will be faced. The research on electrostatic discharge protection devices and circuits with high reliability and strong electrostatic protection performance plays an important role in improving the yield and reliability of integrated circui...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L27/02H01L27/088H01L21/8234
CPCH01L27/088H01L21/823481H01L27/0262H01L27/0296H01L29/0649H01L29/0615H01L29/0684
Inventor 李燕妃孙家林朱少立谢儒彬顾祥吴建伟洪根深贺琪
Owner 58TH RES INST OF CETC
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