Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Integrated anti-radiation high-voltage SOI device and manufacturing method thereof

A manufacturing method and anti-radiation technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., to achieve the effects of increasing the opening threshold, improving the anti-single event latch-up ability, and reducing the transport coefficient

Active Publication Date: 2021-07-02
58TH RES INST OF CETC
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The object of the present invention is to provide an integrated radiation-resistant high-voltage SOI device and its manufacturing method to solve the problem of ESD devices in the radiation-resistant high-voltage CMOS process proposed in the background art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Integrated anti-radiation high-voltage SOI device and manufacturing method thereof
  • Integrated anti-radiation high-voltage SOI device and manufacturing method thereof
  • Integrated anti-radiation high-voltage SOI device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] The invention provides an integrated anti-radiation high-voltage SOI device, the structure of which is as follows figure 1 As shown, it includes a P-type substrate 11, a buried oxide layer 21, and an N-type epitaxial layer 13 formed in sequence; the surface of the N-type epitaxial layer 13 is provided with a high-voltage NMOS device 71, a high-voltage PMOS device 72, and a high-voltage ESD device 73; The integrated radiation-resistant high-voltage SOI device also includes an isolation oxide layer 22, a gate oxide layer 23, a pre-metal dielectric layer 24, a first P-type doped region 41, a second P-type doped region 42, and a third P-type doped region. 43. Fourth P-type doped region 44, fifth P-type doped region 45, first N-type doped region 31, second N-type doped region 32, polysilicon 51, polysilicon gate electrode 52, source metal Electrode 61, drain metal electrode 62, anode metal electrode 63, cathode metal electrode 64; the first N-type doped region 31 is set in t...

Embodiment 2

[0042] The invention also provides a method for manufacturing an integrated radiation-resistant high-voltage SOI device, which is processed and prepared on a silicon-on-insulator material, such as figure 2 As shown, the silicon-on-insulator has a P-type substrate 11, a buried oxide layer 21 and a top layer of silicon 12 stacked sequentially from bottom to top, including the following steps:

[0043] Such as image 3 As shown, the ion implantation process is used to implant P-type impurities on the top layer silicon 12 to form the first P-type doped region 41; the implantation dose of the first P-type doped region 41 is 1E13~1E15cm -2 ;

[0044] Such as Figure 4 As shown, an N-type epitaxial layer 13 is formed on the buried oxide layer 21 by using an epitaxial process; the N-type epitaxial layer 13 covers the first P-type doped region 41;

[0045] Such as Figure 5 As shown, a deep silicon trench is etched on the N-type epitaxial layer 13 by photolithography and etching p...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an integrated anti-radiation high-voltage SOI device and a manufacturing method thereof, and belongs to the field of semiconductors. Third P-type doped regions are simultaneously formed in the high-voltage PMOS device and the high-voltage ESD device, the trigger voltage of the high-voltage ESD device is determined by the junction breakdown of the third P-type doped regions and the N-type epitaxial layer, and the junction breakdown design can be carried out according to the working voltage of the circuit. According to the integrated high-voltage ESD device, the third P-type doped regions are introduced to the surface of the second P-type doped region, so that the base region concentration of a parasitic triode NPN device is increased, the base region transport coefficient is reduced, and the high-voltage ESD device is started in advance under the condition of avoiding single-particle radiation, thereby improving the single-particle latch-up resistance of the device and improving the maintaining voltage of the device. The first P-type doped region on the buried oxide layer reduces the parallel resistance of the emitter junction of the parasitic NPN triode and improves the opening threshold of the parasitic NPN triode, thereby further improving the single event latch resistance of the ESD device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an integrated radiation-resistant high-voltage SOI device and a manufacturing method thereof. Background technique [0002] Electrostatic discharge phenomenon widely exists in nature, and it is one of the important reasons for the failure of integrated circuit products. Integrated circuit products are easily affected by electrostatic discharge during their manufacturing and assembly processes, resulting in reduced reliability or even damage to the product. Electro-Static Discharge (ESD device) design is an important part of integrated circuit reliability design, and with the development of integrated circuit technology, it will face more challenges. Research on electrostatic discharge protection devices and circuits with high reliability and strong electrostatic protection performance has a non-negligible role in improving the yield and reliability of integrated circuits....

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L27/02H01L27/088H01L21/8234
CPCH01L27/088H01L21/823481H01L27/0262H01L27/0296H01L29/0649H01L29/0615H01L29/0684
Inventor 李燕妃孙家林朱少立谢儒彬顾祥吴建伟洪根深贺琪
Owner 58TH RES INST OF CETC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com