An erasing method of a single-grid non-volatile memory

Abstract

The invention discloses an erasing method of a single-grid non-volatile memory. The non-volatile memory is provided with a single floating gate structure, when erasing operation is carried out, voltage is applied to a drain electrode, voltage is not applied to a gate electrode, a reverse layer is generated and controlled through the drain electrode voltage, and therefore the erasing voltage is reduced, the erasing speed is increased, and the problem of excessive erasing can be prevented.

Description

technical field [0001] The present invention relates to a kind of non-volatile memory (Non-Volatile Memory), in particular to a kind of oxide layer (oxide) thickness greater than 100 Angstroms that can be used in high pressure process An erasing method for single-gate non-volatile memory for erasing storage elements. Background technique [0002] Currently, Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application specific integrated circuits (ASICs). Today, with the development of computer information products, Electronically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read Only Memory, EEPROM) has the function of electrically writing and erasing data due to its non-volatile memory function, and when the power is turned off The final data will not disappear, so it is widely used in electronic products. [0003] Non-volatile memory is programmable to store charge to change the ...

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Problems solved by technology

Therefore, in the structure of the known non-volatile memory, in addition to the gate layer of the transistor, an additional conductive layer needs to be added to store charges, and a double-layer structure is formed. There are more steps in the process of film deposition, etching, exposure and development, etc., which increase the cost, complicate the process, reduce the yield of components, and increase the man-hours, especially when used in embedded (Embedded) EEPROM products.

[0004] In the known erasing method for EEPROM components, the stored charge is moved from the floating gate to the transistor under the tunneling effect of the Fowler-Nordheim (Fowler-Nordheim) tunneling (referred to as F-N tunneling) technology. In addition, the voltage often needs to be greater than 10V, and because the structure of the single-gate EEMPROM memory is transistor substrate-floating gate-capacitor substrate, the stored charge can be released to any direction according to the direction of the electric field; resulting in a single-gate Over-erasing of EEPROM components becomes more serious

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