Two-bit memory cell and its circuit structure for in-memory computing

A circuit structure and storage unit technology, applied in the field of in-memory computing circuit architecture, storage array architecture field, can solve problems affecting neural network system power consumption, computing accuracy and reliability, reliability problems, erasing and writing interference, etc. problems, to achieve the effect of increasing density, increasing the number of connections, and preventing excessive erasure

Active Publication Date: 2020-12-15
NANJING UCUN TECHNOLOGY INC
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Problems solved by technology

[0007] Existing in-memory computing circuits based on SONOS or Floating Gate technology use transistors to bind charge storage weights, but their storage cell technology has serious reliability problems after the weight order is too high or the number of weight erasures increases, which is manifested as erasure. Phenomena such as interference and leakage current generated by over erase affect the power consumption, operation accuracy and reliability of the neural network system

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  • Two-bit memory cell and its circuit structure for in-memory computing
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  • Two-bit memory cell and its circuit structure for in-memory computing

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[0027]In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0028] It should be noted that the terms "comprising" and "having" in the description and claims of the present invention and the above drawings, as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, including a series of steps or units A process, method, device, product or device is not nec...

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Abstract

A double-bit storage unit structure and its array structure and circuit structure in an in-memory computing chip. The double-bit storage unit includes three transistors, and the three transistors are connected in series, a selection transistor is used as a switch in the middle, and two charge storage transistors are arranged symmetrically on both sides. The storage array composed of the double-bit storage unit is used to store the weight of the neural network, and the multiplication and accumulation operation of the neural network is performed through a two-step current detection method. The invention can effectively control leakage current, realize higher weight storage density and stronger reliability, and further realize neural network operation with more practical significance.

Description

technical field [0001] The invention relates to the field of memory unit and in-memory computing chip circuit design, in particular to a double-bit memory unit structure, a memory array architecture based on the double-bit memory unit structure, and a circuit architecture applied in the field of in-memory computing. Background technique [0002] Deep neural network is one of the perception models with the highest level of development in the field of artificial intelligence. It simulates the neural connection structure of the human brain by establishing a model, and describes the data characteristics hierarchically through multiple transformation stages, providing images, videos, audios, etc. Large-scale data processing tasks bring breakthrough progress. A deep neural network model is a computational model that consists of a large number of nodes connected through a mesh structure, and these nodes are called neurons. The connection strength between every two nodes is express...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/063G11C7/10G11C7/12G11C7/18G11C8/08G11C8/14
CPCG06N3/063G11C7/1051G11C7/1078G11C7/12G11C7/18G11C8/08G11C8/14G11C11/54G11C7/1006G11C7/062G11C7/067G11C2207/063G11C16/26G11C16/08G11C16/0441G06N3/065G06N3/02G11C11/56G11C16/0483
Inventor 林小峰丛维
Owner NANJING UCUN TECHNOLOGY INC
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