Chip packaging method and chip packaging structure

Abstract

The invention provides a chip packaging method and a chip packaging structure. A thermal expansion coefficient transition layer with a relatively low thermal expansion coefficient is formed on the component wafer and exposed to the surface of the reserved position for chip stacking, which can avoid the impact of the encapsulation layer on the component wafer. The wafer on the circle and the thermal expansion coefficient transition layer encapsulation cause a large thermal expansion coefficient mismatch, which can improve the wafer warpage and stress-induced delamination problems, and avoid stacked wafers and encapsulation layers from components Wafer is peeled off to improve the performance of the packaging structure; further, the thermal expansion coefficient transition layer is formed of a solder resist material for a printed circuit board, which is easy to implement, does not produce side effects, and can enhance the adhesion with the subsequent encapsulation layer. Adhesion, to avoid the encapsulation layer from peeling off the surface of the component wafer.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a chip packaging method and a chip packaging structure. Background technique [0002] Chip on wafer (CoW) packaging technology, as one of the advanced packaging (Package) technologies, can stack multiple different The size of the wafer (Die, that is, a block with complete functions cut out from the wafer) to meet different functions, and then realize the manufacture of three-dimensional semiconductor integrated circuit (IC) products. CoW packaging technology has many advantages, such as the ability to achieve high integration of semiconductor devices, reduce the size of semiconductor packages, reduce the cost of final products, simplify assembly processes, and improve yields. After the level injection molding step is completed, problems of wafer warpage and stress-induced delamination are often encountered, which easily cause the stacked chips to peel of...

AI Technical Summary

Problems solved by technology

CoW packaging technology has many advantages, such as the ability to achieve high integration of semiconductor devices, reduce the size of semiconductor packages, reduce the cost of final products, simplify the assembly process and improve yield, etc. After the level injection molding step is completed, problems of wafer warpage and stress-induced delamination are often encountered, which easily lead to the peeling of the stacked wafers from the component wafers, seriously affecting the performance of the packaging structure

Images