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473results about How to "Promote stratification" patented technology

Two-horizontal-movement one-rotation three-freedom-degree series-parallel vibrating screen

The invention discloses a two-horizontal-movement one-rotation three-freedom-degree series-parallel vibrating screen. The two-horizontal-movement one-rotation three-freedom-degree series-parallel vibration screen comprises a supporting frame, a transverse excitation device, a screen body, a rotation excitation device, a vertical excitation device, auxiliary limiting chains, springs, lifting ring bolts and a hopper. A material box frame is arranged on the supporting frame, the screen body is suspended on the supporting frame through the springs and the lifting ring bolts, the transverse excitation device, the rotation excitation device and the vertical excitation device can make the screen body vibrate transversely in a reciprocating mode, swing around the horizontal axis in a reciprocating mode and vibrate vertically in a reciprocating mode, and the auxiliary limiting chains are used for limiting the movement freedom degree of the screen body and improve the movement stability. The screen body can achieve two-horizontal-movement one-rotation three-freedom-degree vibration at most, magnitudes, frequencies, screen surface leaning angles, freedom degrees and other parameters in all directions can be adjusted, the screening efficiency is high, and the handling capacity within per unit interval is large, and the two-horizontal-movement one-rotation three-freedom-degree series-parallel vibrating screen has the advantages of being compact in structure, stable and reliable in working, low in equipment cost and running power consumption, easy to control and the like.
Owner:江门市新会区金昌矽砂有限公司

Wafer level chip size package and manufacturing method thereof

The invention discloses a wafer level chip size package and a manufacturing method of the wafer level chip size package, belonging to the field of sensors. The wafer level chip size package comprises a wafer, wherein the positive surface of the wafer is a first surface which forms an image sensing region, the negative surface of the wafer is a second surface, and the first surface comprises a microlens, a metal interconnection layer and an optical interaction region from top to bottom; a silicon through hole which does not penetrate through a silicon substrate and a redistribution region are manufactured on the first surface, and I/Os at the periphery of the optical interaction region are connected with the silicon through hole; the wall of the silicon through hole is manufactured into a passivation layer and is filled; a polymer material is manufactured into a second protective layer on the redistribution region; the first surface is in bonding with a glass sheet, and a cavity is formed between the glass sheet and the wafer; the second surface is thinned and forms a groove structure through an etching process, and the silicon through hole is exposed; a line layer is manufactured on the second surface, and the silicon through hole is connected to a solder pad cushion; a welding prevention layer is manufactured on the line layer, and the solder pad cushion is exposed; and a solder ball is arranged on the solder pad cushion. With the adoption of the wafer level chip size package and the manufacturing method of the wafer level chip size package, the technological process is reduced, the reliability and the production efficiency of a product are improved, and the production cost is lowered.
Owner:BEIJING UNIV OF TECH

Method for comprehensively recovering aluminum electrolysis waste cathode carbon blocks through ultrasonic-assisted floatation and pressure acid leaching

The invention relates to a method for comprehensively recovering aluminum electrolysis waste cathode carbon blocks through ultrasonic-assisted floatation and pressure acid leaching, and belongs to the technical field of comprehensive utilization of aluminum electrolysis solid waste resources. The method comprises the steps of carrying out ultrasonic pretreatment after crushing and grinding the aluminum electrolysis waste cathode carbon blocks, carrying out floatation on pretreated powder to obtain electrolyte residues and carbon residues, and reusing the wastewater of floatation; removing carbon impurities after the electrolyte residues are subjected to microwave heating to obtain electrolyte powder with high purity, and carrying out pressure acid leaching on the carbon residues to remove solvend so as to obtain carbon powder with high purity; and carrying out absorption treatment on the gas generated during acid leaching with alkali liquor, carrying out evaporative crystallization on filter liquor to separate out sediment of sodium salt and aluminum salt, and reusing distilled water. According to the method, through collaborative assistance action among ultrasonic pretreatment, floatation, microwave heating and pressure acid leaching, the high-efficiency comprehensive recycling of aluminum electrolysis waste cathodes is achieved. The method for comprehensively recovering aluminum electrolysis waste cathode carbon blocks through ultrasonic-assisted floatation and pressure acid leaching is reasonable in technological design, high in recovery rate of valuable matter, high in processing capacity, short in production cycle, high in purity of obtained products, free of secondary pollutants and applicable to industrial large-scale application.
Owner:CENT SOUTH UNIV

Large chip scale package and manufacturing method thereof

The invention provides large chip scale package and a manufacturing method thereof and belongs to the technical field of sensors. An optical interaction region is arranged at the center above a silicon substrate in a first surface of a wafer, one side provided with the optical interaction region is connected with a metal interconnection structure, and an input-output (I/O) around the optical interaction region on the silicon substrate is connected to an electrode pad through the metal interconnection structure. The surface of the metal interconnection structure is provided with a protective layer, and a stepped protrusion or groove structure is formed on the protective layer. The first surface of the wafer is bonded with a glass piece together, and a cavity is formed between the glass piece and the wafer. A second surface of the wafer is provided with a through silicon via (TSV) hole, the electrode pad penetrates through the silicon substrate through the TSV hole to be connected to a bonding pad on the second surface of the wafer, a passivation layer and a metal liner are sequentially manufactured on a hole wall of the TSV hole, and a polymer material is filled into the TSV hole. An anti-welding layer is manufactured on the second surface of the wafer, and a weld ball is manufactured on the bonding pad. By means of the large chip scale package and the manufacturing method, the layering problem of glass and the silicon substrate in an existing package structure is solved, and the packing reliability is improved.
Owner:BEIJING UNIV OF TECH
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