Wafer level chip size package and manufacturing method thereof
A wafer-level chip and size packaging technology, which is applied in semiconductor/solid-state device manufacturing, radiation control devices, electrical components, etc. Problems such as layer phenomenon, to improve product reliability, production efficiency, improve warpage, and reduce costs
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Example Embodiment
[0038] The present invention enhances the bonding force between the glass 250 and the wafer 200 by making a stepped protrusion or groove structure on the first surface 201 of the wafer, thereby improving the problem of delamination between the glass and the wafer, and improving the reliability of packaging. It is flexible and suitable for larger CIS packages. At the same time, the second surface 202 of the wafer is etched to form a trench structure, which reduces the demand for high aspect ratio through silicon vias (TSV). figure 2 A schematic diagram of a CIS package with a stepped protrusion structure made on the first surface 201 of the wafer drawn according to an embodiment of the present invention.
[0039] To figure 2 As shown, the wafer level chip scale package (WLCSP) of the embodiment of the present invention includes a wafer 200, the front side of the wafer 200 is the first surface 201 forming the image sensing area, and the negative side of the wafer 200 is the firs...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap