Wafer level chip size package and manufacturing method thereof

Abstract

The invention discloses a wafer level chip size package and a manufacturing method of the wafer level chip size package, belonging to the field of sensors. The wafer level chip size package comprises a wafer, wherein the positive surface of the wafer is a first surface which forms an image sensing region, the negative surface of the wafer is a second surface, and the first surface comprises a microlens, a metal interconnection layer and an optical interaction region from top to bottom; a silicon through hole which does not penetrate through a silicon substrate and a redistribution region are manufactured on the first surface, and I / Os at the periphery of the optical interaction region are connected with the silicon through hole; the wall of the silicon through hole is manufactured into a passivation layer and is filled; a polymer material is manufactured into a second protective layer on the redistribution region; the first surface is in bonding with a glass sheet, and a cavity is formed between the glass sheet and the wafer; the second surface is thinned and forms a groove structure through an etching process, and the silicon through hole is exposed; a line layer is manufactured on the second surface, and the silicon through hole is connected to a solder pad cushion; a welding prevention layer is manufactured on the line layer, and the solder pad cushion is exposed; and a solder ball is arranged on the solder pad cushion. With the adoption of the wafer level chip size package and the manufacturing method of the wafer level chip size package, the technological process is reduced, the reliability and the production efficiency of a product are improved, and the production cost is lowered.

Description

technical field [0001] The present invention relates to a wafer level chip scale package and a method of manufacturing said wafer level chip scale package. The packaging structure and manufacturing method described above can be preferably used for image sensors or MEMS devices. Background technique [0002] Wafer-level packaging (WLP) is a type of IC packaging. As an advanced packaging technology, all process steps are completed before the wafer is sliced. Wafer-level chip-scale packaging (WLCSP) is a combination of wafer-level packaging (WLP) and chip-scale packaging (CSP). Packaging, and on-wafer interconnect bumping and testing. It is precisely because this packaging is different from the traditional packaging method (cutting first and then packaging and testing), wafer-level chip-scale packaging (WLCSP) not only significantly reduces the packaged volume size, reduces packaging costs, and improves packaging efficiency. And more in line with the requirements of high-den...

AI Technical Summary

Problems solved by technology

Third, the package structure shown cannot be used with lower cost wafer-level processing and surface mount technologies

For the CIS packaging structure that uses glass-to-wafer bonding, the larger viewing area will lead to more and more serious delamination between the glass and the silicon substrate.

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