Method and system for obtaining simulation waveform of FPGA software verification results based on uvm

Abstract

The invention discloses a UVM-based method and system for obtaining simulation waveforms of FPGA software verification results, and relates to the field of FPGA software verification. The method includes monitoring the signal of the FPGA software to be tested, and judging whether the signal meets a preset trigger event. And generate the measurement interval information of the FPGA software under test according to the trigger event, use the EDA digital simulation tool to simulate the program of the FPGA software under test, obtain the simulation file, select the corresponding interval in the simulation file according to the measurement interval information The simulation data of the measurement interval is generated to generate the simulation waveform diagram of the measurement interval. A UVM-based FPGA software verification result simulation waveform acquisition method and system provided by the present invention, by monitoring the signal of the FPGA under test, preset trigger events, and automatically generate the measurement interval information of the FPGA software under test according to the trigger conditions. After the completion, the waveform files of each verification moment can be automatically generated through the software.

Description

technical field [0001] The invention relates to the field of FPGA software verification, in particular to a UVM-based method and system for obtaining simulation waveforms of FPGA software verification results. Background technique [0002] UVM is Universal Verification Methodology (UVM), which is a verification platform development framework based on SystemVerilog class library, covering from module level to chip level, ASIC to FPGA, and control logic, data path to processor Verify the entire scene of the subject. [0003] At present, verification engineers often need to spend a lot of energy writing reference models to confirm the verification results when performing verification. The verification result is judged by comparing the expected result at the verification time with the output result of the DUT, which mainly includes observing the waveform diagram at the verification time or printing the relevant signal data at the verification time. The method of observing the ...

AI Technical Summary

Problems solved by technology

The method of observing the waveform diagram at the verification time requires the verification engineer to manually capture the waveform diagram at the verification time on the EDA digital simulation tool. This method will consume a lot of labor and time costs. In the case of a large design scale, the workload will be Unbearable; and the way to print the relevant signal data at the verification moment is not intuitive

[0004] Currently, UVM is widely used in the fields of IC verification and FPGA testing, but there is no method to automatically obtain the simulation waveform diagram of the verification results, which makes the verification work cumbersome. Therefore, it is urgent to design an automatic verification result based on UVM. Method of Simulating Waveform Diagram

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