Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Digital circuit function modeling method and system based on internal entity state transition

A digital circuit and state transfer technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as difficult automatic generation of incentives, poor applicability and scalability, and inability to model and describe digital circuit functions. Achieve good scalability and applicability, avoid redundancy, and facilitate engineering applications

Active Publication Date: 2019-05-14
NAT UNIV OF DEFENSE TECH
View PDF4 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These description methods have problems such as inability to model complex data calculation functions, poor applicability and scalability, and lack of timing-related function descriptions, and cannot achieve complete and efficient digital circuit function modeling and description based on functional specifications.
At the same time, the above method does not use the unified modeling of the functional behavior of the circuit and the entity of the circuit, which leads to incomplete modeling and difficulty in automatically generating incentives.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Digital circuit function modeling method and system based on internal entity state transition
  • Digital circuit function modeling method and system based on internal entity state transition
  • Digital circuit function modeling method and system based on internal entity state transition

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0026] Such as figure 1 As shown, the implementation steps of the digital circuit function modeling method based on internal entity state transition in this embodiment include:

[0027] 1) Analyze and extract function points and internal entities according to the functional specification of the target digital circuit;

[0028] 2) Use the stage transition model with functional attribute classification to formally describe the behavior flow of the function points, and use the extended finite state machine to formally describe the internal entities of the circuit, so as to obtain the stage transfer model and the extended finite state machine. Functional model of the target digital circuit;

[0029] 3) Output the stage transfer model and expand the finite state machine.

[0030] see figure 1In this embodiment, the digital circuit function modeling method based on internal entity state transition specifically adopts a stage transition model with functional attribute classificati...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a digital circuit function modeling method and system based on internal entity state transition. According to the invention, functional points and internal entities are analyzed and extracted according to the functional specifications of the target digital circuit; and performing formalized description on the behavior process of the function point by adopting a stage transfer model with function attribute classification, and performing formalized description on the internal entity of the circuit by adopting an expansion finite state machine, thereby obtaining a functionmodel of a target digital circuit formed by the stage transfer model and the expansion finite state machine. According to the invention, the time sequence characteristic of each functional point in the digital circuit and the concurrent characteristic of multi-functional point execution can be efficiently and completely described; The method is suitable for function modeling of a digital circuit,has the advantages of being formalized and graphical, has good expansibility and applicability, and is convenient to carry out engineering application in the integrated circuit design verification process, especially in the aspect of excitation automatic generation.

Description

technical field [0001] The invention relates to the field of integrated circuit design verification, in particular to a digital circuit function modeling method and system based on internal entity state transfer, which can be used for automatic work of integrated circuit design and verification. Background technique [0002] With the continuous development of social information technology and the continuous improvement of integrated circuit technology, the design scale and functional complexity of integrated circuits continue to increase, which has caused great difficulties in the design and functional verification of autonomous controllable chips. In order to alleviate this problem, the method of modeling and describing the circuit function based on the circuit function requirement specification has good scalability and can greatly improve the development efficiency of software and hardware in the design cycle. At the same time, this method can also be applied to the verifi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCY02E60/00
Inventor 陈书明吕昭王耀华张廷荣胡春媚黎余亮
Owner NAT UNIV OF DEFENSE TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products