Method and device for achieving variable bit width division method through FPGA

Abstract

The invention provides a method for achieving a variable bit width division method through an FPGA, and the method comprises the steps: S1, decomposing a divisor into n segments, calling a basic bit division unit, dividing a decomposed first segment by a dividend, and obtaining a first quotient and a first remainder of the first segment; S2, combining the first remainder with a second segment divisor, and continuously dividing by the dividend to obtain a second quotient and a second remainder of the second segment; splicing the second remainder and the third segment divisor, and dividing the second remainder and the third segment divisor by the dividend to obtain a third quotient and a third remainder of the third segment; and S3, repeating the process until the nth quotient and the nth remainder are obtained, the nth remainder being the remainder obtained by the variable bit width division method, the splicing of the n segments of quotients from the first quotient to the nth quotientbeing the quotient obtained by the variable bit width division method, and ending the operation. According to the method for achieving the variable bit width division method through the FPGA, divisionoperation of any bit width can be achieved, and compared with a traditional method, the shifting division method is greatly improved in speed.

Description

technical field [0001] The present disclosure relates to the field of FPGA, in particular to a method and device for implementing variable bit width division by FPGA. Background technique [0002] Now, with the rapid development of chip manufacturing technology, the scale of FPGA chips is getting larger and faster, and FPGA chips have been used as the core computing components of boards and cards in various occasions, such as aerospace, military industry, communication, artificial intelligence, etc. Smart etc. With its flexible and powerful parallel computing capabilities, FPGA undertakes a large amount of computing work in board applications. How to realize mathematical operations faster and more efficiently has become the direction of FPGA engineers. [0003] Among various complex mathematical operations, there are a large number of addition, subtraction, multiplication, and division. Since FPGAs have built-in DSP units specially used for calculations, addition, subtract...

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Problems solved by technology

Therefore, this method cannot achieve efficient operation

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