Design method of FPGA IP core

Abstract

The invention provides a design method of an FPGA IP core, and the method comprises the steps: carrying out the first evaluation of FPGA IP core resources according to the design of a predetermined user, and determining a first evaluation result; And designing the FPGA IP core according to the first evaluation result. According to the method and the device, the process for evaluating the resourceoccupancy rate designed by the predetermined user is added to the IP design process in the prior art, and the layout wiring result and the resource occupancy rate are given, so that a reasonable IP core resource scale and arrangement can be given according to the design of the predetermined user, and the redundancy of resources in the IP core is avoided.

Description

technical field [0001] The invention relates to the technical field of design of an embedded field programmable gate array IP core, in particular to a design method of an FPGA IP core. Background technique [0002] Field Programmable Gate Array (FPGA) is a large-scale programmable device consisting of programmable logic blocks (CLBs), wiring resources, input and output blocks (IOBs) and other IP resources (such as memory, digital signal processors, etc.) Composition, which provides users with the ability to program or reconfigure the system. [0003] Embedded FPGA (embedded FPGA, eFPGA) is to embed one or more FPGAs into chips such as ASIC, ASSP or system on chip (SoC) in the form of IP. Embedding FPGAs in SoCs in the form of IP can overcome the disadvantages of limited bandwidth of independent FPGAs and fixed functions of ASICs, as well as the problem of passing data between them. The FPGA IP embedded in the ASIC provides the SoC system with the ability to dynamically adj...

AI Technical Summary

Problems solved by technology

After designing the IP core according to the estimated resource scale, when the resources occupied by the user's design exceed the maximum resource of the IP core, the layout and routing of the user's design will fail, and the parameters of the IP core need to be re-determined, resulting in an extension of the design cycle ; In addition, when the resources occupied by the design are far lower than the maximum resources of the IP, the resource occupancy rate of the IP core will be too low, resulting in resource redundancy and an increase in the area of ​​the IP core

Images