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A clock synchronization method, system and device for an Ethernet electrical port

A clock synchronization, Ethernet technology, applied in the field of network communication, can solve the problem that the electrical port module cannot recover the clock signal, etc.

Active Publication Date: 2020-05-29
WUHAN TELECOMM DEVICES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the above defects or improvement needs of the prior art, the present invention solves the problem that the original electrical port module cannot recover the clock signal from the line side and the data side respectively, and transmit the recovered clock signal to the next-level equipment

Method used

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  • A clock synchronization method, system and device for an Ethernet electrical port
  • A clock synchronization method, system and device for an Ethernet electrical port
  • A clock synchronization method, system and device for an Ethernet electrical port

Examples

Experimental program
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Embodiment 1

[0029] In network data transmission, the existing pluggable electrical port module has a built-in crystal oscillator, so the signal transmitted to the line side does not carry the clock signal of the system side, but the clock signal generated by the built-in crystal oscillator of the electrical port module. The signal is not necessarily completely synchronized with the system-side clock signal. Even if the electrical interface module includes a PHY capable of recovering the clock on the line side, since the SFP gold finger of the electrical interface module does not define clock input pins and clock output pins, it does not have the function of recovering clock signals from the system side. This embodiment provides a way to restore the clock signal of the Ethernet electrical port from the system side and the line side, which ensures the synchronization of the clock signals on the system side and the line side connected to the electrical port module, and ensures that clock synchr...

Embodiment 2

[0047] In network data transmission, in some cases, the data sending end and receiving end on both sides of the electrical port need to work in Master-Slave mode to achieve communication function requirements such as command distribution, parallel control, and error monitoring.

[0048] In an Ethernet data communication system, in order to facilitate multi-device communication or management, generally there is only one Master terminal, and there may be multiple Slave terminals. Therefore, when synchronizing Ethernet clocks, the clock at the Master end is generally used as the system operating clock, and the operating clocks at the Slave end and other devices in the system are calibrated.

[0049] In some application scenarios of this embodiment, two systems exist simultaneously in the network: the first system and the second system.

[0050] The first system and the second system are respectively in one of the Master and Slave modes in the Master-Slave mode, and the two system...

Embodiment 3

[0074] In network data transmission, in some cases, when the systems on both sides of the communication work in Master-Slave mode, the related interface devices such as PHY also need to set the working mode to be consistent with the working mode of the local system. Realize synchronous communication.

[0075] In some actual usage scenarios of this embodiment, the first system works in the Master mode, and both the first FPGA and the first PHY also work in the Master mode. At this time, the first FPGA and the first PHY can directly obtain the system clock of the first system to calibrate their own working clock, and pack the clock signal into the communication data packet, and transmit it to the slave end, so that the slave end device can Perform clock synchronization calibration.

[0076] In some actual usage scenarios of this embodiment, the first system works in the Slave mode, and both the first FPGA and the first PHY also work in the Slave mode. When communicating with t...

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Abstract

The invention relates to the field of network communication, in particular to an Ethernet electric port clock synchronization method, system and device. The Ethernet electric port clock synchronization method comprises the following steps that when a system receives data, a PHY and an FPGA on the local side restore clock signals in a received data packet, convert the data packet into SGMII data containing the restored and calibrated clock signals and send the SGMII data to the system; when the system sends data, the SGMII data which are sent by the MAC of the system and contain clock signals are recovered and transmitted step by step through the FPGA and the PHY on the local side, are converted into data packets containing the clock signals and are transmitted to the line side. According to the invention, the FPGA is integrated in the electric port module; the clock recovery and data transmission functions of the FPGA are utilized; the FPGA is used for extracting, recovering and transmitting the clock signals in the SGMII data, so that the synchronous clock signals can be transmitted and recovered among a plurality of communication systems along with data packets, and the purpose of electric port clock synchronization is achieved on the basis of not changing original external interfaces and communication protocols of an electric port module.

Description

【Technical field】 [0001] The invention relates to the field of network communication, in particular to an Ethernet electrical port clock synchronization method, system and device. 【Background technique】 [0002] In recent years, pluggable electrical port modules are very popular in data and access applications. The electrical port modules can be directly inserted into the corresponding slots of the switch, which is convenient for maintenance and system expansion. The electrical port module has a built-in crystal oscillator. The MAC data is transmitted to the module, and the built-in PHY chip of the module packs the SGMII data stream into an Ethernet frame, and after isolation and transformation processing, it is output to the network cable on the line side for transmission. The Ethernet frame data on the line side is connected to the isolated transformer network through the network cable, and after being sent to the MDI layer and PCS layer of the PHY, it is transmitted to th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06
Inventor 张春艳袁涛龙汉波高繁荣吕向东
Owner WUHAN TELECOMM DEVICES
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