Processing technology of SOC chip IP clock in DFT

Abstract

The invention discloses a processing technology of an SOC chip IP clock in a DFT. The processing technology comprises the following steps of carrying out DFT scanning chain testing on an IP clock; introducing a clock control circuit to a DFT scanning chain testing circuit so as to output a multi-bit control signal; introducing this signal to the corresponding IP clock; placing an SOC chip on an ATE base station so that a probe on the ATE base station is contacted with a SOC chip; and after an ATPG tool generates a specific test vector, testing the SOC chip on the ATE base station according tothe test vector. By using the processing technology of the SOC chip IP clock in the DFT, at least two OCC modules are required, and a requirement to a chip port is reduced. Simultaneously, each clockdomain interconnection timing path can be measured and a testing coverage rate is increased. A clock control circuit is merged and the number of inserted cell is reduced so that the testing coverage rate can be increased maximumly. Usage is convenient and the technology is convenient for popularization.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testability design and scan link testing, in particular to a processing technology of SOC chip IP clock in DFT. Background technique [0002] With the rapid development of integrated circuit design and technology, the IP cores integrated by SOC chips are becoming more and more complex, especially in high-speed interfaces such as DDR and PCIE. One of the manifestations of the high complexity of these IP designs is that they have multiple clock domains and multiple clock ports; and this is a clock domain, some have clock paths (timing paths), and some do not. Therefore, under the requirement of high test coverage in DFT design, the processing of these IP clocks is very important. [0003] In the high test coverage of DFT design, usually the clocks of the same frequency are connected together and processed by the same OCC (on chip clock) on-chip clock unit. However, there is a large timi...

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Problems solved by technology

However, there is a large timing path between the clocks, which is difficult to satisfy, causing the scan chain test of the chip to fail.

[0004] Another method is to insert OCC on each clock, but the timing path between OCC circuits cannot be measured, which will lead to a decrease in test coverage, and because multiple OCCs are used, the requirements for chip ports are also great; In the case of insufficient ports, this method will not work

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