A verification system for improving digital circuit function verification efficiency

Abstract

The invention provides a verification system for improving the digital circuit function verification efficiency. According to the verification system, the Zynq ULtraScales + MPSoC EG Devices are mainly adopted as a verification platform to carry out the corresponding verification operation, the verification operation can realize the effective separation of a software layer and a hardware layer inan execution process, while the separated hardware layer only needs to be compiled once, and even if the software layer is changed, the hardware layer does not need to be compiled again, so that the trouble that the hardware layer needs to be compiled when high-level language compiling excitation is changed each time due to the fact that the software layer and the hardware layer are not separatedis avoided. In addition, the verification system also designs and uses a protocol bridge and a verification stimulus with repeated availability, which improves the transportability of the verificationsystem. Under the condition that a protocol bridge with repeated availability or verification excitation can be directly utilized by a new tested design DUT, the establishment period of a new verification system is greatly shortened, and therefore the function verification period of the tested design DUT is shortened.

Description

technical field [0001] The invention relates to the technical field of integrated circuit test verification, in particular to a verification system for improving the efficiency of digital circuit function verification. Background technique [0002] At present, integrated circuits are widely used in different fields. Due to the technical specificity of different fields, in order to improve the applicability and scene specificity of integrated circuits in different fields, corresponding ASICs (Application Specific Integrated Circuits) have been developed. Circuit, ASIC) and a system-on-chip (System-on-Chip, SoC) chip, the application-specific integrated circuit ASIC and the system-on-chip chip together form the core component of the control circuit. As the requirements for the scalability of integrated circuit devices in terms of control and response functions continue to be raised, the functional complexity and circuit scale of the application specific integrated circuit ASIC...

AI Technical Summary

Problems solved by technology

[0003] The existing functional verification methods for digital chips include software simulation-based functional verification, hardware accelerator-based verification and field programmable array FPGA prototype verification. Among them, software simulation-based functional verification is the most widely used verification method. In particular, the functional verification based on the universal verification methodology UVM is the most commonly used, but the functional verification based on software simulation requires a large number of verification stimuli in the design of multi-functional and large-scale systems, and it takes days to run these verification stimuli. Unit calculation, so the verification period of this type of verification method is long; the equipment used for verification based on hardware accelerators is expensive, which prevents it from being widely promoted to many users or R&D teams, and the new version of custom-designed chips for hardware accelerators is also expensive. A lot of time; based on field programmable array FPGA prototype verification, designers need to use hardware description language HDL to realize almost all feature verification. Even simple verification stimulus modification requires re-synthesis and adaptation of the entire chip design, and modification of verification stimulus The process of re-synthesis and adaptation is also time-consuming and error-prone

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