A phase frequency detector with a wide traction range

Abstract

The invention discloses a phase frequency detector with a wide traction range. The trigger circuit comprises first to fourth triggers, first to fourth latches, a first exclusive-OR gate (X1), a secondexclusive-OR gate (X2), a third exclusive-OR gate (X4), a fourth exclusive-OR gate (X6), a first inverter (X3), a first XNOR gate (X5), a second XNOR gate (X7), a first NOR gate (X8), and a second NOR gate (X9), in which data input terminals of the first to fourth flip-flops are connected to clk0, clk45, clk90, and clk135 respectively, and clock input terminals of the first to fourth flip-flops are connected to input data; the output end of the first NOR gate (X8) is connected to the node Fdn, and the output end of the second NOR gate (X9) is connected to the node Fup. According to the method, PD cycle slip is reduced, the traction range of the PD is expanded, an independent FD loop is eliminated, the traction range, clock jitter and data jitter performance of a CDR system are optimized,and noise and system instability caused by back-and-forth switching of circuit control power between a phase frequency loop and a phase discrimination loop in the CDR are avoided.

Description

technical field [0001] The invention relates to a frequency and phase detector with wide traction range, which belongs to the technical field of analog circuits. Background technique [0002] Clock data restorers are widely used in various high-speed serial communication systems, including optical fiber communication, high-speed serial interface communication and interconnection communication between high-performance chips, etc., and are mainly responsible for generating Clock and retimed recovery of data. Frequency detector FD (Frequency Detector) and phase detector PD (PhaseDetector) are important modules in CDR. FD is responsible for generating the clock signal corresponding to the serial data, and PD is responsible for phase alignment of the clock signal and serial data, so that the clock can retime and recover the data at the best sampling point. [0003] The pulling range, clock jitter, and data jitter of a CDR module directly reflect the performance of the module. ...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a frequency and phase detector with a wide pulling range, and solve the problem that the traditional full-rate DFF PD cannot reduce the frequency difference between the data and the clock, resulting in a narrow pulling range. small problem

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