Microprocessor architecture level soft error susceptibility assessment method
A microprocessor and architecture technology, applied in the detection of faulty computer hardware, function inspection, etc., can solve the problem of inaccurate evaluation results of soft error susceptibility, and achieve the effect of improving accuracy
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specific Embodiment 1
[0032] according to figure 1 and figure 2 As shown, the present invention provides a method for assessing soft error susceptibility at the microprocessor architecture level. An analysis module, the method comprising the steps of:
[0033] Step 1: Select a simulator, initialize the simulator through the parameter configuration module, and simulate the function and performance of a specific microprocessor;
[0034] Step 2: judging whether the analyzed component is an instruction queue, a register update unit, a load store queue, or a non-storage component of a functional unit;
[0035] Step 3: The simulator loads the program in the test program module. When the program is running, the command analysis module is used to analyze the command executed in the analyzed component. According to whether the command execution result will affect the subsequent execution of the program, the command Divided into ACE instructions and un-ACE instructions, among them, logical masking instru...
specific Embodiment 2
[0039] According to the different structural characteristics of the microprocessor simulated by the simulator, this method can be applied to the soft error susceptibility analysis of microprocessors with different pipeline structures.
specific Embodiment 3
[0040] The soft error susceptibility analysis process of the present invention comprises the following steps:
[0041] Step 1, simulator initialization configuration: select a simulator, such as the simplesim-ARM simulator in SimpleScalar that targets the ARM instruction set, and initialize the configuration file of the simulator to simulate the complete functions of the microprocessor. The instruction set used in it is ARMv7.
[0042] Step 2, whether it is a non-storage component: judge whether the analyzed component is a non-storage component such as an instruction queue, a register update unit, a load-store queue, a functional unit, etc., and jump to step 3; otherwise, jump to step 6;
[0043] Step 3, instruction analysis module: the ACE bit refers to the bit that must be guaranteed to be correct in order to ensure that the execution process does not go wrong during the running of the program. Correspondingly, the un-ACE bit means that even if a soft error occurs on this bit...
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