19 results about "Microprocessor architecture" patented technology

The invention provides a microprocessor architecture, a clock signal generation method and a storage medium, and is applied to the technical field of computers, the microprocessor architecture comprises a control unit, a clock signal source and a function unit, and the clock signal source comprises a basic clock unit and a frequency modulation clock unit. The frequency modulation clock unit comprises a first gating unit and at least two parallel initial signal generation units, the control unit configures first configuration information and first gating information, and the basic clock unit generates a basic clock signal; each initial signal generation unit generates a respective corresponding initial clock signal according to the first configuration information and the basic clock signal, and the first gating unit determines a target clock signal in each initial clock signal according to the first gating information and outputs the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. The clock signal source provided by the invention can effectively simplify the adjustment process of the clock frequency, improve the adjustment efficiency of the clock frequency, and meet the actual application requirements.

This application provides a security monitoring method and a microprocessor architecture. The method is applied to a microprocessor architecture including a processor core and a security monitoring module. The security monitoring module includes a ring oscillator with adjustable inverter stages. The method includes: when the security monitoring module detects a change in the process corner of the ring oscillator, it adjusts the inverter stages of the ring oscillator according to the current process corner of the ring oscillator and the operating frequency of the monitored module, so that the operating frequency of the ring oscillator is consistent with the operating frequency of the monitored module. The monitored module includes any module in the microprocessor architecture, and the ring oscillator serves as a reference frequency source for security monitoring of the monitored module. The above method can provide a stable reference frequency within the microprocessor architecture, thereby improving the accuracy and effectiveness of security monitoring of the monitored module.

The application provides a memory performance test method and device, a microprocessor architecture and a storage medium, and is applied to the technical field of computers. After obtaining a memory mapping request of a user state program, the method obtains target page table attributes associated with a target file descriptor carried by the memory mapping request and allocates target physical memory. Then, the method configures page table entries of a memory page table according to the target page table attributes, establishes address mapping between the target physical memory and a virtual address space in the memory page table, and finally feeds back address information of the virtual address space to the user state program, so that the user state program performs memory testing based on the obtained address information. The file descriptor is associated with target page table attributes preconfigured by the user state program. By initiating a memory mapping request carrying different file descriptors, virtual address spaces mapped according to different page table attributes can be obtained, the test process is greatly simplified, the flexibility of the test process is improved, and the test efficiency is improved.

The invention relates to the technical field of communication, in particular to a data transmission method for a double-microprocessor architecture, which is applied to the double-microprocessor architecture, the double-microprocessor architecture comprises a main microprocessor and an auxiliary microprocessor, and comprises the following steps: an upper computer sends a data packet to the main microprocessor, and when the main microprocessor receives the data packet, the main microprocessor sends the data packet to the auxiliary microprocessor; the method comprises the following steps: analyzing and identifying a data packet, acquiring a handshake character string of a handshake character in the data packet, when the handshake character string is a first character string, caching the data packet by a main microprocessor and sending the data packet to an auxiliary microprocessor, and completing corresponding operation according to the data packet after the main microprocessor and the auxiliary microprocessor correctly and completely receive the data packet. Through cascade operation between the upper computer and the double-microprocessor architecture, data transmission of the double-microprocessor architecture and the upper computer is diversified, upgrading of the main microprocessor and the auxiliary microprocessor can be met, hardware resources are not occupied, and cost is reduced.

The application is suitable for the field of microprocessor architecture, on-chip multi-core system and embedded real-time computing technology, and provides a fine-grained cache partition lock method based on RISC-V extension instruction and a processor, the method comprising: adding a Zicpl extension instruction family in the RISC-V instruction set architecture, the Zicpl extension instruction family comprising a LOCK.CP instruction, an UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction; adding a partition lock table on the cache controller side of the processor, the partition lock table comprising a plurality of entries, each entry comprising an owner field, a timeout field and a valid field; adding a lock flag and a partition identification field in the Tag area of the cache memory; the application can significantly improve the real-time performance and system energy efficiency, and has significant industrial and economic value.

The invention provides a locking detection circuit, a phase-locked loop and a microprocessor architecture, which are applied to the technical field of computers, the circuit comprises a first time delay module, a second time delay module, a first sampling module, a second sampling module and a detection module, the first time delay module receives a first signal of the phase-locked loop, and the second time delay module receives a second signal of the phase-locked loop; the first delay module receives a first signal of the phase-locked loop and outputs the first signal as a first sampling clock after delaying the phase of the first signal according to a first preset delay duration, and the second delay module receives a second signal of the phase-locked loop and outputs the second signal as a second sampling clock after delaying the phase of the second signal according to a second preset delay duration; the first sampling module samples the first signal according to the second sampling clock to output a first sampling signal, the second sampling module samples the second signal according to the first sampling clock to output a second sampling signal, and the detection module determines that the phase-locked loop is locked when the first sampling signal and the second sampling signal correspond to the same level. Locking detection of the phase-locked loop is achieved, and it is ensured that the phase-locked loop provides a stable clock signal.

This utility model relates to microprocessor technology, biometric identification systems, and embedded intelligent devices designed for automatic personal recognition based on multiple biometric characteristics. The proposed utility model is a multimodal microprocessor-based biometric identification device comprising a fingerprint scanner, a voice identification module, a microprocessor computing module, a memory module, a neural network data processing unit, a decision-making unit, a communication interface, and a power source. A distinctive feature of the utility model is its use of a unified microprocessor architecture, enabling local intelligent processing of multiple biometric modalities without the need to transmit data to external computing servers.The microprocessor computing module collects, digitally filters, extracts features, analyzes, and compares user biometric data with templates stored in the device's memory. Fingerprints and voice characteristics are used as biometric features. Combined processing of multiple biometric parameters improves identification accuracy, reduces the likelihood of false positives and false negatives, and enhances the system's resilience to external influences and noise. The technical result of this utility model is increased reliability, speed, and autonomy of biometric identification through the use of integrated microprocessor processing of multimodal biometric data and recognition algorithms.The utility model can be used in access control and management systems, banking and financial systems, mobile devices, medical information systems, critical infrastructure facilities, government personal identification systems, and intelligent IoT systems. The proposed device is compact, capable of autonomous operation, offers high data processing speeds, and can be integrated into modern digital security systems.

This invention discloses an operator-based microprocessor architecture design method and system. The invention includes: for a target instruction set architecture, determining the computational functions contained in the target instruction set it supports, and abstracting these computational functions as operators; for each operator in the operator set, establishing execution component libraries for the instructions of the target instruction set's computational functions mapped to those operators; and updating the execution pipeline template based on the execution component library to complete the design of the execution pipeline in the target instruction set architecture. This invention effectively reduces the coupling between the instruction set and the hardware architecture corresponding to the pipeline execution stage, enabling rapid completion of the execution pipeline design in the target instruction set architecture. It provides a lightweight and scalable implementation method for microprocessor design supporting multiple instruction sets, alleviating the area overhead problem caused by incremental design of multiple instruction sets, and reducing the design cycle of microprocessor architecture upgrades.

The invention provides a clock signal acquisition device and a microprocessor architecture. The clock signal acquisition device comprises a plurality of groups of regional signal acquisition modules and a global clock selection module, wherein each physical region of the microprocessor architecture is provided with a group of region signal acquisition modules; one group of regional signal acquisition modules comprises at least one local clock selection module and one regional clock routing module; the local clock selection module collects clock signals of all functional modules in a physical area, selects a first clock signal from the collected clock signals and sends the first clock signal to the area clock routing module; the regional clock routing module selects a second clock signal from the received first clock signals and sends the second clock signal to the global clock selection module; and the global clock selection module at least selects a third clock signal from the received second clock signals and outputs the third clock signal. The device can realize efficient acquisition of clock signals in the microprocessor architecture through simple wiring and structure.

The invention provides a clock tree and an arrangement method thereof, a microprocessor architecture and electronic equipment, and is applied to the technical field of computers, the clock tree comprises a first-level trunk and at least one second-level trunk, the first-level trunk is arranged based on an H-tree architecture and comprises at least one first-level Tap point, and the second-level trunk comprises at least one second-level Tap point; the secondary trunk comprises a first intensifying buffer and at least one secondary branch driven by the first intensifying buffer, the first intensifying buffer serves as a starting point of the secondary trunk and is connected with a first-stage Tap point of the primary trunk, and the secondary branch is used for providing a clock signal for a local clock network of the microprocessor architecture and is connected with a second-stage Tap point of the secondary trunk. According to the clock tree provided by the invention, only one level of trunk is established based on the H-tree architecture, so that the proportion of the H-tree structure in the clock tree can be effectively reduced, the use quantity of the enhanced buffers is reduced, the overall power consumption and the performance loss of the clock tree are reduced, and the current design requirements of low power consumption and high reliability on the microprocessor architecture are met.

The invention provides a transaction monitoring device which is integrated with a network interconnection module and / or a function module in a microprocessor architecture in a bypass logic mode, and an interface and a buffer unit are arranged in the network interconnection module and / or the function module. The transaction monitoring device is used for monitoring information of an upstream module and / or a downstream module flowing through the interface and the buffer unit, and performing conjoint analysis on interface message monitoring data and buffer unit monitoring data obtained by monitoring so as to perform fault detection; wherein the upstream module comprises an initiator of a transaction request, and the downstream module comprises a processor responding to the transaction request. The transaction monitoring device can comprehensively and accurately monitor the transaction interaction process between the modules in the microprocessor architecture, and can realize accurate fault detection.

This application provides a write circuit, memory, and microprocessor architecture, applicable to the field of computer technology. The circuit includes an input data latch circuit and an adaptive drive circuit. The input data latch circuit receives and latches an input signal in response to a write clock signal, and outputs a first output signal and a second output signal. In response to a first level triggering write in the first clock signal, the adaptive drive circuit drives the write bit line to a first target level and drives the complementary write bit line to a second target level according to the first and second output signals. In response to a second level prohibiting write in the first clock signal, the adaptive drive circuit drives the write bit line and the complementary write bit line to a precharge level. This circuit omits the write bit line precharge circuit and column select circuit in related technologies, eliminates the influence of NMOS transistors in the column select circuit, and drives the write bit line pairs up and down, thereby improving the write capability and write speed of the memory cell.

The invention is suitable for the technical field of microprocessor system structures, on-chip multi-core systems and embedded real-time computing, and provides a fine-grained cache partition locking method and processor based on RISC-V. The method comprises the steps that a Zicpl extension instruction family is newly added in an RISC-V instruction set system structure, and the Zicpl extension instruction family comprises a LOCK.CP instruction, a UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction; a partition lock table is additionally arranged on the cache controller side of a processor, the partition lock table comprises a plurality of entries, and each entry comprises an owner field, a timeout field and a valid field; adding a lock flag bit and a partition identification field in a Tag region of the cache memory; the real-time performance and the system energy efficiency can be remarkably improved, the compatibility of software and hardware and the feasibility of large-scale mass production are considered, and remarkable industrial and economic values are achieved.

The invention provides a load current waveform extraction method, electronic equipment and a storage medium, which are applied to the technical field of computers, and the method comprises the steps: carrying out the operation test of a simulation circuit model of a microprocessor architecture through a preset test set, and obtaining an initial load current waveform of the microprocessor architecture; waveform fragment extraction is carried out on the initial load current waveform by using a plurality of different time windows to obtain target current waveform fragments corresponding to the time windows, and finally each target current waveform fragment is determined as a target load current waveform of the microprocessor architecture. Because the duration of the time window is related to load current components of the initial load current waveform at different frequencies, the method utilizes a plurality of different time windows to carry out waveform fragment extraction on the initial load current waveform, can obtain load current waveforms corresponding to different frequency bands, and further comprehensively measures the load characteristics of the microprocessor architecture. The accuracy and reliability of PI simulation are improved, and the simulation test requirement is met.

The invention provides an output jitter suppression circuit, a signal processing circuit and a microprocessor architecture, the circuit comprises a clock regulation module and a first sampling module, and an automatic zeroing comparator operates according to a sampling clock output by the clock regulation module and outputs a first output signal; the first sampling module samples the first output signal according to the sampling clock and outputs a second output signal to the load circuit, and the clock adjusting module outputs the first sampling clock when the second output signal is not detected to jitter and outputs the second sampling clock when the second output signal is detected to jitter. The sampling process is periodically triggered according to the sampling clock, so that the probability that the first sampling module acquires a jittering signal peak of the first output signal is reduced, and sampling is performed at the lower clock frequency under the condition that the second output signal jitters; the probability of collecting the signal peak is further reduced, and the jitter of the output signal of the automatic return-to-zero comparator is effectively inhibited.

The invention provides a microprocessor architecture, a clock signal generation method and a storage medium, the microprocessor architecture comprises a control unit, a clock signal source and a function unit, and the clock signal source comprises an initial clock unit and a frequency modulation unit. The initial clock unit generates at least two initial clock signals according to first configuration information configured by the control unit, the frequency modulation unit works in a voltage domain range corresponding to the function unit, and the frequency modulation unit comprises a first gating unit and at least two time sequence sensors; the time sequence sensor feeds back time sequence characteristic parameters when corresponding initial clock signals are transmitted in corresponding voltage domain ranges, and the control unit configures first gating information according to the time sequence characteristic parameters and indicates the first gating unit to output target clock signals in the initial clock signals to the functional unit. The frequency modulation process is based on time sequence characteristic parameters monitored in real time, the maximum performance is explored by fully utilizing time sequence margins under different working voltages, and the performance and the energy consumption ratio of the microprocessor architecture are improved.

The invention provides a power consumption model construction method, a power supply integrity evaluation method, electronic equipment and a storage medium, which are applied to the technical field of computers, and the method comprises the following steps: after obtaining input data for performing dynamic power consumption analysis on a microprocessor architecture, inputting the input data into a first analysis tool to obtain a load current curve; according to the method, the load current curve and the parasitic parameter file are generated through different tools, the data size needing to be processed by a single tool is reduced, and the power consumption model of the microprocessor architecture is obtained. The operation efficiency of a single tool is improved, the time for generating a load current curve and a parasitic parameter model is shortened, and the load current curve and a parasitic parameter file can be synchronously generated, so that the overall time required for creating a chip power consumption model is effectively shortened, the test efficiency is improved, and the simulation test requirement is met.

This application provides a dual-power memory and microprocessor architecture, applicable to the field of computer technology. The memory includes a memory array, a read operation circuit, and a write operation circuit. The write operation circuit includes a first level conversion circuit. The memory array and the subsequent circuit of the first level conversion circuit operate in a first voltage domain. The read operation circuit and the preceding circuit of the first level conversion circuit operate in a second voltage domain. The first level conversion circuit converts the signal output by the preceding circuit from the voltage amplitude of the second voltage domain to the voltage amplitude of the first voltage domain. The subsequent circuit is connected to the memory cell. This circuit only places the memory cell and the subsequent circuit in the first voltage domain and sets the read operation circuit in the second voltage domain. The read operation circuit does not involve the conversion between different voltage domains, thus eliminating the need for the level conversion circuit. The area overhead and readout delay caused by the level conversion circuit are eliminated, which helps to improve the data readout efficiency of the dual-power memory.

The invention provides a microprocessor architecture, which is applied to the technical field of computers, the microprocessor architecture comprises a processor core, a power consumption control unit and a controlled unit, the power consumption control unit comprises a register module and a plurality of control units, the register module comprises a plurality of register groups, each register group corresponds to one control unit, and each register group corresponds to one control unit. The control unit is connected with the controlled unit, and the power consumption control unit can execute low-power-consumption processing operation originally executed by the processor core, so that the workload of the processor core can be effectively reduced, the low-power-consumption processing operation is prevented from occupying resources of the processor core, and the running performance of the processor core can be improved. Furthermore, the power consumption control unit supports switching of two working modes, the first processing mode or the second processing mode can be selected according to the actual situation of the microprocessor architecture in actual application, more options are provided for the low-power-consumption processing process, and application requirements in different scenes are met.