Four-pin integrated circuit packaging structure with heat dissipation

Abstract

The invention provides a four-pin integrated circuit packaging structure with heat dissipation, which comprises an encapsulation structure composed of a base island, a lead pin, a heat dissipation pinand a plastic packaging body. The packaging structure is used for packaging a device with three to four ports. Gaps are reserved between a PIN1 and a PIN2, and between a PIN1 and a PIN2 and a PIN4 and the base island, thereby improving the voltage withstanding ability. The PIN3 is connected with the base island, the pin width is increased, laying of a grounding wire is facilitated, heat generatedwhen a chip works can be radiated through the PIN3 exposed outside, and the chip can be prevented from being overheated and burnt down. Each flow channel of the frame can be molded with four lead frame units left and right, and the molding compound utilization rate is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit packaging, in particular to an integrated circuit packaging structure with four pins for heat dissipation. Background technique [0002] Chip packaging is a technology that packs integrated circuits with insulating plastic or ceramic materials. It not only plays the role of placing, fixing, sealing, protecting chips and enhancing thermal conductivity, but also serves as a bridge between the internal world of the chip and the external circuit. With the development of smart products and wearable devices in the direction of smaller, thinner and lighter, the manufacturing process of chips is also developing from the micron level to the nano level. However, the lower the size of the chip manufacturing process, the more difficult it is. The advanced 10nm process is approaching the limit of what the equipment can achieve. If the equipment wants to be made smaller, thinner, and lighter, it can ...

AI Technical Summary

Problems solved by technology

With the development of smart products and wearable devices in the direction of smaller, thinner and lighter, the manufacturing process of chips is also developing from the micron level to the nano level. However, the lower the size of the chip manufacturing process, the more difficult it is. The advanced 10nm process is approaching the limit of what the equipment can achieve. If the equipment wants to be made smaller, thinner, and lighter, the only way to find a breakthrough is through packaging technology.

[0003] The current chip packaging SOP&SSOP has gradually been unable to meet the needs of smaller chips for signal transmission speed, anti-interference ability, and heat dissipation performance in terms of pin spacing and product thickness. It is necessary to develop smaller and thinner chips. Encapsulation form, the present invention proposes just in order to achieve this purpose

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