CAN bus controller data storage circuit and data storage method

Abstract

The invention discloses a CAN bus controller data storage circuit and a data storage method. Data interaction between a CAN core data buffer area and an e-mail box is achieved by arranging an information processing module; the register and the mailbox access module realize information interaction between the processor and the mailbox; the RAM access arbitration module controls access to the mailbox; a dual-port RAM is adopted, the dual-port RAM is divided into 128 mailboxes, and for any one sending mailbox, if the sending ID and frame information do not need to be changed, only the data bit needs to be updated each time under the control of an information processing module; for one receiving mailbox, after the received data is read out by the processor, the processor can reconfigure the IDand the mask bit of the received data through the mirror image register, so that the mailbox can receive data of a new ID node; the mailboxes are numbered to store the data, so that the processor canclearly know which mailbox the data comes from, and ID decoding is not needed.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to a CAN bus controller data storage circuit and a data storage method. Background technique [0002] The currently widely used CAN bus controller chip is the SJA1000 chip produced by PHILIPS. This chip sets the node receiving ID and ID mask code (mask) in reset mode, and uses a FIFO with a capacity of 64 bytes to store the receiving data. Use 13 registers with a bit width of 8 bits to form a data buffer, which is shared by sending and receiving. When sending, since the sending and receiving share the buffer, in addition to writing new frame data into the sending buffer each time, the frame information and frame ID must also be written into the sending buffer, even if the frame information and ID sent twice exactly the same. When receiving, the processor reads the received data including frame information, frame ID and frame data from the FIFO through the recei...

AI Technical Summary

Problems solved by technology

The third is that if a node receives data from multiple nodes, all node data will be stored together indiscriminately, and the processor needs to decode the frame ID for each frame of data read back to determine that the frame data comes from Where, then you can determine how to deal with it, causing a large programming burden on the processor when applying

The fourth is that the capacity of the receiving FIFO is too small. If an extended frame of 8 bytes of data is received, a maximum of 4 frames of data can be stored. When receiving continuously, if the processor cannot read the data in time, it is easy to cause FIFO overflow

For these four drawbacks, what kind of data storage method can be used to make users more convenient and concise when using it? After searching relevant literature, there is still no good solution

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