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Low-delay video splicing method, device and system

A video splicing and low-latency technology, applied in the field of video splicing, can solve problems such as large surgical movements, inconvenient operation for doctors, and patient injuries

Active Publication Date: 2019-07-09
NANJING JUSHA DISPLAY TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the delay of the video image is too large, it will bring inconvenience to the doctor, and even lead to excessive operation, causing unnecessary damage to the patient

Method used

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  • Low-delay video splicing method, device and system
  • Low-delay video splicing method, device and system
  • Low-delay video splicing method, device and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0064] This embodiment is a low-latency video splicing method, refer to figure 1 As shown, the methods include:

[0065] Obtain parallel input signals of multiple channels of video, and detect the input refresh rate of each video signal and video input signal timing data; video input signal timing data includes the total number of lines of a frame of video input signal and the effective number of lines of a video input signal ;

[0066] Scaling each channel of video signals according to a preset ratio, and writing the scaled each channel of video signals into the buffer unit respectively;

[0067] Obtain the video fusion instruction information, the video fusion instruction information includes the output refresh rate of each video after fusion and video output signal timing data; the video output signal timing data includes the total number of lines of a frame of video output signal , the effective number of lines of a frame of video signal after scaling is ;

[...

Embodiment 2

[0092] This embodiment is a low-latency video splicing device, including:

[0093] The video input signal acquisition and detection module is used to obtain parallel input signals of multiple channels of video, and detect the input refresh rate of each video input signal and video input signal timing data;

[0094] The video scaling and buffer writing module is used to scale each video signal according to a preset ratio, and write the scaled video signals into the buffer unit respectively;

[0095] The video fusion command analysis module is used to obtain video fusion command information, and the video fusion command information includes the output refresh rate of each video after fusion and video output signal timing data;

[0096] The optimal read first address generation module is used to write the address based on the current cache and the input refresh rate , video input signal timing data, output refresh rate And video output signal timing data to generate the c...

Embodiment 3

[0103] This embodiment is a low-latency video splicing system, refer to image 3 As shown, the system includes a video input module, a video routing module, a video signal processing module and a control module;

[0104] The video input module includes a plurality of video input channels, each video input channel respectively receives video input signals and converts the video signals into high-speed serial signals; each video input channel is respectively provided with a video input unit and a high-speed serial signal conversion unit 1 in turn, The video input unit is used to receive a video input signal to be spliced ​​together, and convert the received signal into a parallel signal; the high-speed serial signal conversion unit 1 converts the parallel signal output by the video input unit into a unified high-speed serial signal;

[0105] The video signal received by the video input unit has different signal formats depending on the interface type. The video input unit is an ...

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Abstract

The invention discloses a low-delay video splicing method, device and system, and relates to the technical field of video splicing, and the method comprises the steps: obtaining the input refresh rateof multiple paths of video signals and the time sequence data of video input signals; respectively writing the zoomed video signals into a cache unit; obtaining the output refresh rate of each videoand video output signal time sequence data in the video fusion instruction; based on the current cache write-in address, the input / output refresh rate and the input / output video signal time sequence data, generating an optimal read-out first address of each video; reading a corresponding video signal from the cache unit according to the optimal read head address and the output refresh rate; and carrying out fusion splicing on the read video signals, and outputting and displaying the video signals. According to the invention, the cache unit is arranged to optimize the reading mode of the imagedata, so that the delay of video stitching can be reduced, the output image has better real-time performance and is smoother, and the requirements of medical and other low-delay application scenarioscan be met.

Description

technical field [0001] The present invention relates to the technical field of video splicing, in particular to a low-latency video splicing method, device and system. Background technique [0002] The simultaneous advancement of image acquisition, transmission, display and other technologies has prompted more and more fields, such as medical care, security, education, media, etc., to rely on video to realize real-time information sharing. In most application scenarios, video viewers often need to watch multiple video images, which requires a video splicer to complete the fusion of images in order to watch more video images on a limited display device. [0003] However, video splicers in the medical field have higher requirements - low latency. For example, during the operation, the doctor needs to make a comprehensive decision on the next operation based on the multiple video images he sees. If the delay of the video image is too large, it will bring inconvenience to the ...

Claims

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Application Information

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IPC IPC(8): H04N5/265H04N21/44
CPCH04N5/265H04N21/44004H04N21/44016
Inventor 张玉彬王卫杨乾坤
Owner NANJING JUSHA DISPLAY TECH
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