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Lookup table type convolution operation hardware structure based on FPGA

A hardware structure and convolution operation technology, applied in the field of deep learning, to achieve the effect of simple operation, saving on-chip resources, and avoiding multiplication operations

Inactive Publication Date: 2019-07-26
SUN YAT SEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the technical defect of high resource overhead in the convolution operation kernel provided by the prior art, the present invention provides an FPGA-based lookup table convolution operation hardware structure

Method used

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  • Lookup table type convolution operation hardware structure based on FPGA
  • Lookup table type convolution operation hardware structure based on FPGA
  • Lookup table type convolution operation hardware structure based on FPGA

Examples

Experimental program
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Embodiment 1

[0027] Such as figure 1 As shown, a FPGA-based lookup table convolution hardware structure includes M lookup tables and an adder tree with a shift operation;

[0028] The size of each lookup table is The data of each row in the lookup table is The corresponding address index is x j , where x j =j(0≤j≤2 N -1), stands for x j The value of the i-th bit in the binary expression; a i Indicates the weight data, each lookup table stores the same data, a total of M, M lookup tables are established on the FPGA, and the data is queried in order; the lookup table is based on the input data x i To index the data stored internally, the address input is in means x N The value of the mth bit of , the corresponding output is recorded as s m ;

[0029] An addition tree with a shift operation contains M input nodes and M-1 adder nodes, the input of each node is the output of the lookup table, the size is bit data, output of M lookup tables {s 0 ,s 1 ,s 2 ,...,s M-1} are i...

Embodiment 2

[0033] Such as figure 1 , figure 2 , image 3 , Figure 4 , Figure 5 as well as Figure 6 As shown, an FPGA-based lookup table convolution operation hardware structure includes 8 lookup tables{s 1 ,s 2 ,s 3 ,...,s 8} and an adder tree with shift operations, structured as figure 1 , each lookup table is of size 2 5 ×11, that is, store 2 5 An 11-bit data.

[0034] The data of each row in the lookup table is The corresponding address index is x j . where x j =j(0≤j≤31) stands for x j The value of the i-th bit in the binary expression. The address input for the mth lookup table is The data content stored in the lookup table is as follows figure 2 shown.

[0035] The hardware structure of the lookup table is as follows image 3 shown.

[0036] An addition tree with a shift operation contains 8 input nodes and 7 adder nodes, the input of each node is the output of the lookup table, and the output of the 8 lookup tables {s 0 ,s 1 ,s 2 ,...,s 7} are inp...

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Abstract

The invention relates to a lookup table type convolution operation hardware structure based on a field programmable gate array (FPGA). N multiplication operations in convolution operation are disassembled, N pieces of M-bit data with the same offset are added, the sum of the N pieces of M-bit data is stored in a lookup table, and M lookup tables are formed. After a calculation result of the lookuptable is obtained, the result is sent to an adder tree with shift operation, and a convolution result is calculated. Compared with a traditional method, the hardware consumption of the structure saves more than 50% of LUT resources (FPGA implementation), and the lookup table type convolution operation hardware structure has the advantages of being easy to deploy, convenient to reuse and the like.

Description

technical field [0001] The present invention relates to the technical field of deep learning, and more specifically, relates to a lookup table convolution operation hardware structure based on FPGA (Field Programmable Gate Array). Background technique [0002] Deep convolutional neural networks are widely used in computer vision, image classification, object recognition and other fields, but the huge data sets and complex calculation processes required to train the network limit the platform for network deployment, especially in low power consumption and computing resources. Limited and other platforms, especially mobile devices and embedded devices. Migrating deep convolutional neural networks from server clusters to mobile platforms is a current research hotspot and general trend. [0003] In the convolutional neural network, the calculation of the convolutional layer accounts for more than 90% of the total calculation. Therefore, the acceleration of the convolutional lay...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/04G06F15/78
CPCG06N3/063G06F15/7871G06N3/045
Inventor 黄以华黄文津吴黄涛
Owner SUN YAT SEN UNIV
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