A convolutional neural network computing device and method

Abstract

The invention discloses a convolutional neural network computing device and method. The device includes a neural network model buffer for caching and encoding the convolutional neural network model; a neural network model decoder for reading the encoded model and decoding the model to obtain the model The logical index and control information of the weight; the input neural network feature map buffer is used to cache the pixel value of the input feature map; the feature map storage controller is used to read the feature map pixel value data according to the feature map logical index; the accumulator array is used for Add the input feature map pixel values ​​multiplied by the same neural network model weight value, and generate a temporary accumulation result; the pipeline buffer is used to cache the temporary accumulation result; the multiplication accumulator array is used to compare the temporary accumulation result with the corresponding The weight values ​​of the neural network model are multiplied, and the multiplication results belonging to the current convolution operation are added to generate the pixel value of the output feature map; the output neural network feature map buffer is used to cache the pixel value of the output feature map.

Description

technical field [0001] The present invention relates to the fields of integrated circuits and artificial intelligence, and more specifically relates to a device for accelerating convolutional neural network reasoning operations and a corresponding neural network model encoding method. Background technique [0002] With the rise of deep learning technology, convolutional neural networks are widely used in various fields, such as computer vision, image processing, speech recognition, autonomous robots, driverless cars, etc. As the core algorithm of deep learning technology, convolutional neural network has many advantages such as high reasoning accuracy and strong fault tolerance; however, it also has problems such as huge amount of calculation and consumption of system storage resources. The convolution operation in the convolutional neural network usually consumes more than 90% of the running time of the algorithm. Therefore, in order to realize the real-time calculation of ...

AI Technical Summary

Problems solved by technology

The core of the convolution operation is the multiply-accumulate operation. Therefore, the existing convolutional neural network hardware acceleration circuits adopt a single multiply-accumulate array structure to accelerate the multiply-accumulate operation. This multiply-accumulate array is composed of thousands of identical multiply-accumulate units. , each multiplying and accumulating unit needs a multiplier circuit, and the hardware acceleration circuit of this structure often needs to consume a lot of hardware resources to realize thousands of multiplier circuits, resulting in the disadvantages of high integrated circuit implementation cost and large circuit power consumption.

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