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Method for forming gate structure of three-dimensional memory device

A storage device, three-dimensional technology, applied in the direction of electrical components, electrical solid-state devices, circuits, etc., can solve the problem of high cost

Active Publication Date: 2019-08-13
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly
As a result, the storage density of planar memory cells approaches the upper limit

Method used

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  • Method for forming gate structure of three-dimensional memory device
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  • Method for forming gate structure of three-dimensional memory device

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Embodiment Construction

[0045] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in a variety of other applications.

[0046] Various embodiments according to the present disclosure provide a gate-last process for forming a gate structure of a 3D memory device. In the disclosed method, after forming the multilayer gate structure and before forming the isolation layer (eg, silicon oxide layer) on the sidewall of the slit, an additional isolation layer (eg, a silicon film) may be formed to cover the Exposing the surface of the multilayer gate structure, preventing the exposed surface of the multilayer gate structure from being oxidized during deposition of the s...

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Abstract

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating dielectric stack on a substrate; forming multiple slits, each penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing multiple sacrificial layers in the alternating dielectric stack through the plurality of slits to form multiple trenches; forming a conductive layer in each of the trenches; forming a first isolation layer on sidewalls of the slits to cover the conductive layers to prevent the conductive layers from beingoxidized; forming a second isolation layer on surfaces of the first isolation layer, a material of the second isolation layer being different from a material of the first isolation layer; and depositing a conductive material into the slits to form multiple conductive walls, the conductive walls are insulated from the conductive layers.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Chinese Patent Application No. 201710729505.5 filed on August 23, 2017, the entire contents of which are incorporated herein by reference. technical field [0003] Embodiments of the present disclosure relate to three-dimensional (3D) storage devices and fabrication methods thereof. Background technique [0004] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication methods. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit. [0005] 3D memory architectures can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral components that control signals to and from t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11521H01L27/11551H01L27/11568H01L27/11578H10B41/30H10B41/20H10B43/20H10B43/30
CPCH10B41/20H10B41/30H10B43/20H10B43/30H10B43/35H10B43/27
Inventor 徐强夏志良邵明霍宗亮
Owner YANGTZE MEMORY TECH CO LTD