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Integrated etching optimization method for metal hard mask damascene

An optimization method, a hard technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as inability to conduct circuits, inability to fill in metal, and influence of geometric progression yield, so as to avoid cavity The effect of severe pressure fluctuations, improving the backflow phenomenon, and avoiding pressure fluctuations in the cavity

Active Publication Date: 2021-06-15
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] 1. The metal hard mask Damascus integrated etching often has defects due to pollutants blocking the etching, which eventually leads to the failure of the metal to be filled and the circuit to be unable to conduct
[0004] 2. Metal hard mask Damascus integrated etching wafer position edge blocking etching defect is more serious than the middle phenomenon
[0005] 3. The integrated etching of metal hard mask Damascus will cause the yield rate of geometric progression due to the accumulation of multiple etching layers

Method used

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  • Integrated etching optimization method for metal hard mask damascene
  • Integrated etching optimization method for metal hard mask damascene
  • Integrated etching optimization method for metal hard mask damascene

Examples

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no. 1 example

[0028] The first embodiment of the metal hard mask Damascus integrated etching optimization method provided by the present invention includes the following steps:

[0029] 1) Perform metal hard mask Damascus integrated etching, record the specified parameters of the transmission chamber and the main etching chamber during the preset period, and record the working conditions of the Damascus integrated etching pump body valve during the preset period;

[0030] 2) Record whether there are blocking etching defects or cavity particles after the integrated etching of damascene is completed;

[0031] 3) Perform the above steps 1) and 2) repeatedly, make statistics on the records of the above steps 1) and 2), and extract the valve work of the pump body during the preset period of Damascus integrated etching without blocking etching defects or cavity particles. The condition is used as the standard working condition of the pump body valve;

[0032] 4) When performing metal hard mask D...

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Abstract

The invention discloses a metal hard mask damascene integrated etching optimization method, which includes performing metal hard mask damascene integrated etching, recording specified parameters of a transmission cavity and a main etching cavity at a preset time period, and recording During this preset period, the valve working condition of Damascus integrated etching pump body; record whether there are blocking etching defects or cavity particles after the Damascus integrated etching is completed; perform the above steps repeatedly, and make statistics on the records of the above steps, and the extraction does not occur The working condition of the pump body valve during the preset period of Damascus integrated etching to block etching defects or cavity particles is taken as the standard working condition of the pump body valve; when performing metal hard mask Damascus integrated etching production, the standard working condition of the pump body valve is implemented condition. The present invention avoids severe pressure fluctuations in the cavity by optimizing the control of the valve angle of the pump body, combined with the switching time of the valve body of the pump body, finally reduces the possibility of pollutants in the pump body, and avoids the occurrence of blocking etching defects and particle conditions in the cavity.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a metal hard mask damascene integrated etching optimization method. Background technique [0002] With the reduction of the size of semiconductor devices, in the process technology of 65nm and below, the integrated etching of metal hard mask damascene often has defects that block etching. Part of the reason for this defect is that during the wafer transfer process and during the etching process, due to the fluctuation of the process step conversion pressure, there is air flow disturbance in the chamber, which promotes the surrounding of the chamber, the pump body and the hidden parts in contact with the wafer. Particles fall to the surface of the wafer and eventually form a blocking etch, which prevents the subsequent metal from being filled into it, which will cause the metal circuit to be unable to conduct. While the metal hard mask Damascus integrated etching proces...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/67
CPCH01L21/67253H01L21/7681
Inventor 庄望超
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD