High-linearity delay chain

Abstract

A high-linearity delay chain comprises a calibration module, a delay chain module and a first multiplexer, and the delay chain module comprises 2n-1 cascaded delay units. Each delay unit comprises 2mdelay paths and a second multiplexer, and each delay path outputs an input signal of the delay unit to the second multiplexer after different delays; the second multiplexer selects the signal output after passing through the corresponding delay path according to the m-bit calibration code; the clock end of the calibration module is connected with a clock signal, and the calibration end of the calibration module is connected with the output end of the last cascaded delay unit, and is used for generating m-bit calibration codes, judging whether the calibration codes are added or subtracted by one when the rising edge of the clock signal comes, and transmitting the input signal of the delay chain to the input end of the first delay unit in the delay chain module; input end of first multiplexer is connected with input end of delay chain module and 2n- And the selection end of one delay unit is connected with an n-bit selection signal, and the output end of the delay unit is used as the output end of the delay chain.

Description

technical field [0001] The invention belongs to the technical field of power electronics, and in particular relates to a delay chain with high linearity. Background technique [0002] As modern technology enters the nanometer level, and the integration of circuits is getting higher and higher, and the frequency of circuits is getting faster and faster, so the optimization of timing is becoming more and more important. The delay chain structure is a typical timing structure. There are more and more digital circuits in the delay chain structure, and the requirements for the precision and linearity of the delay chain structure are also getting higher and higher. The delay chain structure has a wide range of applications, and has applications in many different structures such as phase-locked loops, digital pulse width modulators, FPGAs, and DC-DC converters. In the traditional delay chain structure, a single delay unit can only implement two delay paths, and the linearity is no...

AI Technical Summary

Problems solved by technology

[0003] Aiming at the problem of low linearity in the above-mentioned traditional delay chain, the present invention proposes a delay chain, which introduces a multiplexer into a single delay unit, so that the delay unit can realize multiple delays, and at the same time use the same calibration code to control Each delay unit makes the delay time of each delay unit the same, and realizes outputting a delayed signal with high linearity

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