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Semiconductor structure and forming method thereof

A technology of semiconductor and process method, applied in the field of semiconductor structure and its formation, can solve the problem that the formation process of hard mask layer needs to be improved, etc.

Pending Publication Date: 2019-09-13
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, in the existing methods for forming semiconductor structures, the formation process of the hard mask layer for making fins still needs to be improved.

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Embodiment Construction

[0033] It can be seen from the background art that, in the existing semiconductor structure formation method, the formation process of the hard mask layer for forming the fin still needs to be improved.

[0034] Now analyze a method for forming a semiconductor structure. The process steps of forming a semiconductor structure mainly include: providing a substrate; forming a number of discrete first sacrificial layers on the surface of the substrate; Arranged in sequence at equal intervals, the width of the first sacrificial layer is equal; a second sacrificial layer is formed on the sidewalls on both sides of the first sacrificial layer, the width of the second sacrificial layer is equal, and is located adjacent to the The distance between the second sacrificial layer on the opposite sidewalls of the first sacrificial layer is equal to the width of the first sacrificial layer; the first sacrificial layer is removed; after the first sacrificial layer is removed, a A hard mask la...

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Abstract

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate; forming a plurality of discrete first sacrifice layers on one part of surface of the substrate, wherein the first sacrifice layers are sequentially arranged on the substrate at equal intervals and the widths of the first sacrifice layers all are equal andare first widths; forming second sacrifice layers on side walls at two sides of each first sacrifice layer, wherein the intervals between the second sacrifice layers on the opposite side walls of theadjacent first sacrifice layers are second widths and the second widths are not equal to the first widths; removing the first sacrifice layers; forming hard mask layers on the side walls at two sidesof each second sacrifice layer after the first sacrifice layers are removed, wherein the widths of the hard mask layers all are equal; and removing the second sacrifice layers. According to the semiconductor structure and the forming method thereof, the adjacent hard mask layers with unequal intervals can be formed, thereby subsequently forming adjacent fins with unequal intervals.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs has also been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, resulting in poor control ability of the gate to the channel, and short-channel effects (SCE: short-channel effects) more likely to happen. [0003] The Fin Field Effect Transistor (FinFET) has outstanding performance in suppressing the short channel effect. The gate of the FinFET can control the fin at least from both sides. Therefore, compared with the planar MOSFET, the gate of the FinFET has an The control ability is stronger, and the short channel effect can be well suppr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/10H01L29/78
CPCH01L29/66795H01L29/785H01L29/1033
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP