Semiconductor device failure analysis method

Abstract

The invention provides a semiconductor device failure analysis method. The method comprises the following steps of exposing a test area of a semiconductor device, wherein the test area includes a plurality of test points; selecting at least one of the plurality of test points as an input end; forming an input structure electrically connected to the input end; applying a test signal to the input structure; and using an electrical test probe to scan and test the test points except for the input end to which the test signal is applied. Through introducing the new semiconductor device failure analysis method, when a semiconductor device is tested and analyzed by using an electrical probe test method such as a conductive atomic force microscope and the like, input structures electrically connected to the test points are formed. A bias voltage is applied to the test points through the input structures and labor and time cost required for failure analysis can be effectively reduced through the multiple input structures.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a failure analysis method for semiconductor devices. Background technique [0002] As semiconductor devices continue to shrink in size and become more complex, new failure analysis techniques are emerging. Atomic Force Microscopy (AFM) can obtain nanoscale resolution by directly interacting with the sample surface by using a tiny needle tip. Among them, the conductive atomic force microscope (Conductive Atomic Force Microscopy, CAFM) can scan and analyze the current signal of the nanoscale area on the sample surface by introducing a conductive probe. This has broad application prospects in the field of electrical failure analysis such as semiconductor device leakage. [0003] At present, in the process of using CAFM to analyze the leakage of semiconductor devices, it is generally used to apply a bias voltage to the substrate of the sample and use CA...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a failure analysis method for semiconductor devices, which is used to solve the problem of inability to accurately and efficiently apply bias to the test points in the device during the CAFM test in the prior art. pressure problem

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