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Memory testing method and device

A technology of memory testing and virtual memory, which is applied in the field of memory, can solve the problems that production time affects memory development time, etc., and achieve the effects of saving hardware production time, shortening development time, and improving development efficiency

Pending Publication Date: 2019-09-27
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The embodiment of the present invention provides a memory testing method and device to solve the problem in the prior art that the hardware production time of the memory affects the development time of the memory

Method used

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  • Memory testing method and device
  • Memory testing method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0049] figure 1 A flow chart of steps of a memory testing method provided by an embodiment of the present invention is shown. Applied to a terminal, the method includes:

[0050] Step 101, simulating a virtual memory; wherein, the virtual memory includes a virtual front-end interface, an FTL algorithm, and a virtual flash memory.

[0051] In this embodiment, the memory hardware mainly includes a front-end interface, an FTL algorithm and a NAND chip, wherein the FTL algorithm is an important component module in the memory hardware, and the stability of the FTL algorithm determines the stability of the memory firmware. The FTL algorithm mainly maps the logical address to the physical address of the NAND chip. During this process, it will also trigger FTL's garbage collection, wear leveling, bad block management and other mechanisms. Since the FTL algorithm can be realized by software, the virtual memory can be realized by simulating the front-end interface as a virtual front-e...

Embodiment 2

[0059] figure 2 A flow chart of steps of a memory testing method provided by an embodiment of the present invention is shown. Applied to a terminal, the method includes:

[0060] Step 201, simulating a virtual memory; wherein, the virtual memory includes a virtual front-end interface, an FTL algorithm, and a virtual flash memory.

[0061] Step 202, the preset block device driver invokes the virtual front-end interface to analyze the first test instruction, and obtains an analysis result; wherein, the analysis result includes at least an operation instruction, an LBA, and the number of LBAs, and the operation instruction includes At least one of reading, writing and erasing.

[0062] In this embodiment, after receiving the first test instruction, the preset block device driver invokes the virtual front-end interface to analyze the first test instruction and obtain the analysis result. Specifically, the operation instruction, LBA and the number of LBAs are analyzed from the ...

Embodiment 3

[0071] Figure 4 A structural block diagram of a memory testing device provided by an embodiment of the present invention is shown. Deployed at the terminal, the device includes:

[0072] A memory simulation module 301, configured to simulate a virtual memory; wherein, the virtual memory includes a virtual front-end interface, an FTL algorithm, and a virtual flash memory;

[0073] A test command sending module 302, configured to send a first test command to the virtual memory through a preset block device driver;

[0074] A test instruction response module 303, configured for the virtual memory to respond to the first test instruction.

[0075] Optionally, the test command sending module 302 is specifically used for the preset block device driver to invoke the virtual front-end interface to parse the first test command to obtain a parsing result;

[0076] Wherein, the parsing result at least includes an operation instruction, an LBA, and a quantity of the LBA, and the opera...

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Abstract

The invention provides a memory testing method and device. The method is applied to a terminal and comprises the following steps: simulating a virtual memory, wherein the virtual memory comprises a virtual front-end interface, an FTL algorithm and a virtual flash memory; sending a first test instruction to the virtual memory through a preset block device driver; and enabling the virtual memory to respond to the first test instruction. Through the embodiment of the invention, the test of the memory does not depend on the hardware of the memory, the hardware manufacturing time of the memory is saved, the development time of the memory is further shortened, and the development efficiency of the memory is improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a memory testing method and device. Background technique [0002] With the rapid development of information technology, the application of memory is becoming more and more extensive. Since the stability of the memory directly affects the product performance, in order to ensure the quality of the product, a series of tests, such as stress test, speed test, etc., must be performed on the memory. [0003] The traditional test method is to test on the hardware platform after the memory hardware is manufactured. Among them, the hardware production cycle seriously affects the development time of the memory. Contents of the invention [0004] Embodiments of the present invention provide a memory testing method and device to solve the problem in the prior art that the hardware production time of the memory affects the development time of the memory. [0005] In order to solve the abo...

Claims

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Application Information

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IPC IPC(8): G06F11/26
CPCG06F11/261
Inventor 王玺
Owner GIGADEVICE SEMICON (BEIJING) INC
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