Providing single data rate (SDR) mode or double data rate (DDR) mode for the command and address (CA) bus of registering clock drive (RCD) for dynamic random access memory (DRAM)

Abstract

Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.

Description

[0001] Cross reference of related applications [0002] This application claims the pending U.S. Provisional Application No. 62 / 463,896 filed in the U.S. Patent and Trademark Office on February 27, 2017 and the non-provisional application No. 15 / 901,693 filed in the U.S. Patent and Trademark Office on February 21, 2018. Priority of the number, the entire content of the application is incorporated herein by reference. Technical field [0003] The present invention generally relates to the field of command and address (CA) buses of memory devices, and particularly relates to the provision of single data to the command and address (CA) bus of a registered clock driver (RCD) for dynamic random access memory (DRAM) Speed ​​(SDR) mode or double data rate (DDR) mode. Background technique [0004] Dynamic Random Access Memory (DRAM) technology can use double data rate (DDR) mode on the addressing mechanism (for example, the registered clock driver (RCD) from the host's command / address (CA)...

AI Technical Summary

Problems solved by technology

However, the signal integrity of the CA input bus can be severely compromised due to path length, path noise, path attenuation, and path reflections (e.g., impedance mismatch), especially as clock rates increase

[0005] For example, signal integrity degradation may limit clock frequency scaling (i.e., running a clock frequency at a higher rate) to improve overall processing system performance

Also, signal integrity degradation can lead to sub-optimal signal alignment during DRAM initialization

Furthermore, signal integrity degradation may be exacerbated as multiple memory devices (e.g., DRAMs) are installed with a common CA bus, which may increase bus loading and cause further signal integrity degradation

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