Input interface circuit

Abstract

The invention provides an input interface circuit. When the voltage of the gasket is higher than the preset operation voltage, the clamping circuit enables the voltage of the first node to be maintained at the preset operation voltage. The first inverter is coupled between the first node and the second node. The high-voltage buffer circuit adjusts the voltage of the third node according to the gasket voltage and the voltage of the second node, and enables the voltage of the third node and the gasket voltage to increase and decrease in the same voltage change direction. The second inverter is coupled between the third node and the fourth node. The input end of the voltage recovery circuit is coupled to the fourth node, and the output end of the voltage recovery circuit is coupled to the third node and used for selectively coupling the third node to a power line or a grounding line according to the voltage of the fourth node. The third inverter is coupled between the fourth node and theoutput end.

Description

technical field [0001] The invention relates to an input interface circuit for high and low voltage conversion. Background technique [0002] In general, device dimensions in semiconductor manufacturing processes correspond to operating voltages. For example, the default operating voltage of a complementary metal-oxide-semiconductor field-effect transistor (hereinafter referred to as a transistor) manufactured by a 0.35-micron process is 3.3 volts, and that of a transistor manufactured by a 0.18-micron process is 1.8 volts. volt. In order to be compatible with a variety of signal specifications, some circuits design part of their input interface to receive signals higher than the preset operating voltage, such as circuits made with 0.18-micron complementary metal-oxide-semiconductor field-effect transistors Signals with an amplitude of 3.3 volts can be received. [0003] figure 1 An example of an input interface circuit capable of receiving a digital signal twice its pre...

AI Technical Summary

Problems solved by technology

[0006] The disadvantage of the input interface circuit 100 is that at the voltage V P By (VDD-V TH ) to VDD during this period, the transistors MNC1 and MNC2 are not turned on, and the node N 1 So in a floating state

At this time the voltage V 1 is out of control, resulting in a voltage V IN There is considerable uncertainty

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