Data processing method and processing circuit

A processing circuit and data processing technology, which is applied in the field of image processing, can solve the problems of increasing CPU processing load and low processing efficiency, and achieve the effects of reducing CPU load, improving processing efficiency, and efficient outer filling operation

Pending Publication Date: 2019-10-08
SZ DJI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the image processing process, if the above-mentioned outer padding operation is completed by the CPU (Central Processing U

Method used

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  • Data processing method and processing circuit
  • Data processing method and processing circuit
  • Data processing method and processing circuit

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0034] Example 1:

[0035] In the embodiment of the present invention, a data processing method is proposed to realize the function of aligning output with variable input length (such as outer padding operation, such as zero padding operation on the edge of the input feature map), see figure 2 Shown is a schematic flow chart of the data processing method, and the method may include the following steps:

[0036] Step 201: Obtain the first input data and the data length of the first input data. Wherein, the first input data may include but is not limited to: image pixel value; and / or, outer padding pixel value.

[0037] Step 202: Obtain a first value according to the byte offset and the data length. The first value includes N bits, and the value of each bit is the first identifier (such as 1) or the second identifier (such as 0). Each bit corresponds to one storage queue, that is, there are N storage queues, and each bit corresponds to one storage queue.

[0038] In an example, obtain...

Example Embodiment

[0052] Example 2:

[0053] In the embodiment of the present invention, a data processing method is proposed, which can be applied to a processing circuit to realize the function of aligning output with variable input length (such as outer padding operation, such as zero-padded operation on the edge of the input feature map). An asymmetric storage queue structure with variable transmission length and strong scalability.

[0054] See image 3 As shown, the processing circuit may include a first shift sub-circuit, a storage queue, a byte enable sub-circuit, a second shift sub-circuit, and an offset register. The storage queue may be an asymmetric storage queue, such as a FIFO queue. Among them, the number of storage queues is N, and the output data is aligned according to N bytes, that is, the number of storage queues can be configured according to the number of bytes of output data, and the data bit width of each storage queue is 1 byte. The depth is greater than or equal to 2. For...

Example Embodiment

[0076] Example 3:

[0077] On the basis of Embodiment 2, the above data processing method will be described in detail below in conjunction with specific application scenarios. In this application scenario, the number N of the storage queues is 16 as an example for description.

[0078] First, obtain the first input data 0x11, the data length of the first input data is 1, which means that the length of the first input data is 1 byte, that is, 8 bits. The first input data 0x11 can be the image pixel value (ie effective value) of the input feature map, can be the outer padding pixel value of the input feature map (such as the padding value 0), or the image pixel value and outer padding of the input feature map Pixel value, there is no restriction on this.

[0079] Since the data length is 1, the second value is 0000000000000001. If the byte offset currently stored in the offset register is 0, then each bit in the second value is cyclically shifted to the left by 0 bits to obtain the f...

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Abstract

The invention discloses a data processing method and a data processing circuit. The method comprises the following steps: acquiring first input data and a data length of the first input data; a firstnumerical value is obtained according to the byte offset and the data length, the first numerical value comprises N bits, and the value of each bit is a first identifier or a second identifier; obtaining second input data according to the byte offset and the first input data; selecting sub-data corresponding to the bit of which the value is the first identifier from the second input data, and storing the selected sub-data into a storage queue corresponding to the bit; and when the data output condition is met, outputting the sub-data stored in the storage queue. By applying the embodiment of the invention, the external filling operation can be completed by the processing circuit, and the external filling operation does not need to be realized by the CPU, so that the burden of the CPU can be reduced, the external filling operation can be carried out more efficiently, and the processing efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of image processing, in particular to a data processing method and a processing circuit. Background technique [0002] In the process of image processing, padding outside the image is usually involved. For example, see Figure 1A As shown, it is a convolution example without padding (filling), the size of the convolution kernel is 3*3, and the stride (stride) is 1, from Figure 1A It can be found that the size of the input feature map is 5*5, and without padding, the size of the output feature map becomes 3*3. In order to obtain an output feature map of the same size as the input feature map, an outer padding operation can also be performed on the input feature map, for example, a zero padding operation is performed on the edge of the input feature map. For example, see Figure 1B As shown, it is a schematic diagram of adding a zero to each edge of the input feature map; see Figure 1C As shown, it is a s...

Claims

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Application Information

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IPC IPC(8): G06T1/60
CPCG06T1/60G06T1/0007
Inventor 赵尧谷骞韩峰
Owner SZ DJI TECH CO LTD
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