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Layout DRC processing method of integrated circuit conversion process

A processing method and integrated circuit technology, applied in the fields of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as inability to complete, spend a lot of time and energy, and complex layout modification, and achieve the effect of improving work efficiency

Inactive Publication Date: 2019-10-11
SICHUAN CHANGHONG ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually, the design of the conversion process can be quickly completed through APR for the digital part of the layout, but the layout modification after the conversion process of the analog part of the layout becomes very complicated, and hundreds of DRC problems will be encountered, but they are often some simple spacing and line width issues
You can re-use the B process for analog layout design, or modify the DRC problems one by one, but these two methods require a lot of time and effort, and cannot be completed in the short term

Method used

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  • Layout DRC processing method of integrated circuit conversion process
  • Layout DRC processing method of integrated circuit conversion process

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Experimental program
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Effect test

Embodiment 1

[0021] Such as figure 1 As shown, a layout DRC processing method of an integrated circuit conversion process includes the following steps:

[0022] Step 1: Export the layout unit that needs to be modified in the design library of the A process to the GDS file (graphic data flow file) X, and use the DRC check of the B process to check the design rules of the GDS file X;

[0023] Step 2: Filter out the layer set C that meets the DRC check and the layer set D that does not meet the DRC check in the GDS file X;

[0024] Step 3: Create a new design library for process B, and import layer set C in the GDS file X to CELL E in the design library for process B;

[0025] Step 4: Adjust the layer set D in the GDS file X through grammatical operations to make it meet the DRC check of the B process, and output the adjusted layer set D to the GDS file Y;

[0026] Specifically, such as figure 2 As shown, in this embodiment, the contact in the layer set D has the following error: fixedcon...

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Abstract

The invention discloses a layout DRC processing method of an integrated circuit conversion process, which comprises the following steps: A, exporting a layout unit needing to be modified in a design library of a process A to a GDS file X, and checking the GDS file X by using DRC checking of a process B; b, screening out a layer set C meeting inspection and a layer set D not meeting inspection in the GDS file X; C, newly establishing a design library of the process B, and importing the layer set C in the GDS file X into CELL E in the design library of the process B; D, adjusting a layer set D in the GDS file X to meet the DRC check of the process B, and outputting the adjusted layer set D to a GDS file Y. According to the method, the layout DRC problem of the integrated circuit conversion manufacturing process can be solved in batches, the situation that the layout is redrawn or the DRC is manually processed one by one is avoided, and the working efficiency is greatly improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit back-end design, in particular to a layout DRC processing method of an integrated circuit conversion process. Background technique [0002] In the design process of digital-analog hybrid integrated circuits, in order to reduce the power consumption and area of ​​digital circuits, etc., it is necessary to convert the entire design to a smaller feature size process for redesign. Usually, the design of the conversion process can be quickly completed through APR for the digital part of the layout, but the layout modification after the conversion process of the analog part of the layout becomes very complicated, and hundreds of DRC problems will be encountered, but they are often some simple spacing and line width issues. It is possible to re-use the B process for analog layout design, or to modify the DRC problems one by one, but these two methods require a lot of time and effort, and cann...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392G06F30/398
Inventor 陈宏冰姜志强余有勇陶磊李小辉
Owner SICHUAN CHANGHONG ELECTRIC CO LTD