Multi-chip key synchronization method and system and password equipment

A technology of key synchronization and cryptographic equipment, which is applied in the field of information security, can solve problems such as increasing the complexity of business systems and increasing system load, and achieve the effect of improving business processing efficiency and reducing business load

Pending Publication Date: 2019-10-22
中安云科科技发展(山东)有限公司
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  • Application Information

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Problems solved by technology

However, with the increase in the number of cryptographic devices, the complexity of the business system is also increasing, increasing the system load

Method used

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  • Multi-chip key synchronization method and system and password equipment
  • Multi-chip key synchronization method and system and password equipment
  • Multi-chip key synchronization method and system and password equipment

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Embodiment Construction

[0023] The scheme will be described below in conjunction with the accompanying drawings and specific implementation methods.

[0024] figure 1 For a schematic flowchart of a multi-chip key synchronization method provided in the embodiment of this application, see figure 1 , the multi-chip key synchronization method in this embodiment includes:

[0025] S101. The scheduling intermediate unit acquires resource usage rights of the chip.

[0026] Such as figure 2 As shown, the scheduling intermediate unit is responsible for the communication scheduling between the application program and the chip. The scheduling intermediate unit is mainly divided into several levels such as reading configuration files, instruction packaging, obtaining chip resource usage rights, communication layer, and releasing chip resource usage rights. .

[0027] Therefore, before the scheduling intermediate unit in this embodiment obtains the resource usage right of the chip, it first reads the configu...

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Abstract

The invention discloses a multi-chip key synchronization method and system and password equipment, and relates to the technical field of information security. The method comprises the following steps:a scheduling intermediate unit acquiring the resource use right of a chip, setting a synchronization key for each chip in sequence, sending a first key ciphertext generated by a first chip to a second chip in sequence, and completing the key synchronization operation of the chip if the scheduling intermediate unit receives a synchronization success instruction sent back by each second chip; or, if the scheduling intermediate unit does not receive the synchronization success instruction sent back by the third chip, the first chip regenerating the second key ciphertext and sending the second key ciphertext to the second chip in sequence. The chips meeting the service volume can be flexibly selected according to different service requirements, so that the same password equipment can realizeservice processing, the chip of the password equipment does not need to be replaced or the password equipment does not need to be added, the complexity of a service system is not increased, and the maximum improvement of the service processing efficiency is realized through minimum cost increase.

Description

technical field [0001] The present application relates to the technical field of information security, in particular to a multi-chip key synchronization method, system and cryptographic equipment. Background technique [0002] Cryptographic equipment is a general term for devices that have certain cryptographic functions or can complete certain cryptographic tasks. The hardware encryption system can be divided into two parts: cryptographic equipment and interface software. The cryptographic device is the core of the hardware encryption system and the provider of various security service functions. [0003] At present, cryptographic devices in the field of information security are generally divided into three types according to performance: high, medium, and low. Among them, high-end performance is the highest, mid-end performance is average, and low-end performance is the lowest. There is generally only one core cryptographic operation chip inside each cryptographic device...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/12H04L9/08
CPCH04L9/12H04L9/0877
Inventor 郑海森何彬刘磊
Owner 中安云科科技发展(山东)有限公司
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