Method and system for recording working state of digital logic design engineering

A design engineering and digital logic technology, which is applied in the field of recording the working status of digital logic design engineering, can solve problems such as user difficulties, limited signal length, and FPGA debugging work difficulties, and achieve the effect of improving work efficiency and lasting for a long time
CN110471810APending Publication Date: 2019-11-19INSPUR ARTIFICIAL INTELLIGENCE RES INST CO LTD SHANDONG CHINA
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Patent Information

Authority / Receiving Office
CN ยท China
Current Assignee / Owner
INSPUR ARTIFICIAL INTELLIGENCE RES INST CO LTD SHANDONG CHINA
Publication Date
2019-11-19

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Abstract

The invention discloses a method and system for recording the working state of a digital logic design project, and relates to the technical field of digital logic design. Signals needing to be recorded in a design project are marked by using specific marks in a digital logic design file by utilizing a recording circuit; a recording module is used for reading the digital logic design file, retrieving design engineering, finding specific markers, rewriting a digital logic design file and a design engineering top layer file according to the attribute of the marked signal; the recording module isinstantiated, declaration and connection of input and output port signals of the recording module are completed, after digital logic design work of a design project is started, the recording module isused for automatically recording the marked signal state, and the marked signal state is sent to the upper computer through the FPGA for subsequent debugging.
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Description

technical field

[0001] The invention discloses a method and system for recording the working state of a digital logic design project, and relates to the technical field of digital logic design. Background technique

[0002] With the continuous development of silicon technology, the scale of digital logic design is getting larger and larger, and it is becoming more and more difficult to verify the function of the design, and it is difficult to guarantee the completeness of the design. Before ASIC tape-out of the design, performing functional simulation on the FPGA board is an effective measure that can greatly reduce the risk of tape-out failure. Currently FPGA debugging mainly uses the online debugging tools provided by the manufacturer. The signal recording function of the tools requires FPGA on-chip resources as storage, and the length of the stored signals is limited. Observing the changes between signals has brought great difficulties to FPGA debugging.

[0003] The pr...

Claims

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