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Forming method of semiconductor structure

A technology of semiconductor and laminated structure, applied in the direction of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as complex process, and achieve the effect of reducing process steps and process complexity

Inactive Publication Date: 2019-12-06
SHANGHAI IND U TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the process of forming the trench first, the mask pattern for forming the contact hole needs to control the bottom profile, and in the process of forming the contact hole first, the mask for forming the trench needs to cover the contact hole, so both processes have complex processes question

Method used

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  • Forming method of semiconductor structure
  • Forming method of semiconductor structure
  • Forming method of semiconductor structure

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Embodiment Construction

[0022] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0023] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

[0024] If it is to describe the situation directly on ano...

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PUM

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Abstract

The invention discloses a forming method of a semiconductor structure. The method comprises the following steps: forming a laminated structure on a semiconductor substrate; forming a patterned mask layer on the laminated structure; forming a contact hole and a groove in the laminated structure; and forming a second conductive channel and a third conductive channel in the contact hole and the groove, wherein the patterned mask layer comprises a contact hole pattern and a groove pattern corresponding to the first conductive channel, and the heights of the contact hole pattern and the groove pattern are set by the material and height of the first dielectric layer and the second dielectric layer. According to the method provided by the invention, a patterned mask layer is formed by adopting agray-scale photoetching method, a nanoimprint method, a gray-scale mask plate photoetching method or an ion beam gas-assisted deposition method, a semiconductor structure is etched by using dry etching, and patterns of the mask layer are transferred into a laminated structure, so that the process steps are reduced, and the process complexity is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor device manufacturing technology, semiconductor devices already have deep submicron structures. As the number of devices contained in integrated circuits continues to increase, and the size of devices continues to shrink due to the increase in integration, the high-performance, high-density connections between devices are not only performed in a single interconnection layer, but also in multiple layers. interconnection between. Therefore, a multilayer interconnection structure is generally provided in which a plurality of interconnection layers are stacked on each other with an interlayer insulating film interposed therebetween for connecting semiconductor devices. In particular, a multi-layer interconnection structure formed by a dual-damascene proces...

Claims

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Application Information

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IPC IPC(8): H01L21/768
CPCH01L21/76816H01L21/76895H01L21/76897
Inventor 余自强郭贵琦
Owner SHANGHAI IND U TECH RES INST
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