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Wafer-level vacuum integrated packaging structure and manufacturing method thereof

A technology of integrated packaging and manufacturing methods, applied in the field of wafer-level vacuum integrated packaging structure and its manufacturing, can solve the problems of low integration performance, large device volume, high production cost, etc., achieve low cost, small packaging volume, and improve packaging efficiency and cost effects

Active Publication Date: 2019-12-24
SHANGHAI XIANFANG SEMICON CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the field needs to solve the packaging problems of large device volume, low integration performance and high production cost in wafer-level vacuum packaging in the prior art.

Method used

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  • Wafer-level vacuum integrated packaging structure and manufacturing method thereof
  • Wafer-level vacuum integrated packaging structure and manufacturing method thereof
  • Wafer-level vacuum integrated packaging structure and manufacturing method thereof

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Embodiment Construction

[0037] In the following description, the present invention will be described with reference to various embodiments. However, those skilled in the art will recognize that the various embodiments can be implemented without one or more specific details or with other alternative and / or additional methods, materials or components. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of various embodiments of the present invention. Similarly, for the purpose of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, the present invention can be implemented without specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0038] In this specification, reference to "one ...

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Abstract

The invention discloses a wafer-level vacuum integrated packaging structure. The wafer-level vacuum integrated packaging structure comprises a cap wafer; a first wafer to which the cap wafer is hermetically bonded through a first bonding pad, the first wafer includes a device region; and a second wafer, the first wafer being hermetically bonded to the second wafer through a second bonding pad, thesecond wafer includes a cavity facing the device region of the first wafer, and a getter film disposed within the cavity.

Description

Technical field [0001] The invention relates to the technical field of chip packaging, in particular to a wafer-level vacuum integrated packaging structure and a manufacturing method thereof. Background technique [0002] Metal packaging, ceramic packaging, and plastic packaging, these packaging forms are mostly implemented in the form of devices, which are often complicated to assemble, low in efficiency and high in cost. Optical devices or MEMS devices have strict requirements. For example, the design of optical windows requires consideration of window field of view, thickness, AR film, heat dissipation, reliability requirements for materials, requirements for vacuum in the packaging cavity, and what atmosphere to use. [0003] Wafer-level vacuum packaging is an efficient packaging form, especially for wafer-level packaging of array optical devices or MEMS devices. Array-type devices are generally too large in size. If wafer-level vacuum packaging is used, not only the efficienc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81B7/00B81C1/00
CPCB81B7/0032B81B7/0038B81C1/00261B81C1/00269B81C1/00285
Inventor 孙绪燕曹立强
Owner SHANGHAI XIANFANG SEMICON CO LTD