Electrostatic protection element layout structure with high electrostatic discharge tolerance

A technology of electrostatic protection and layout structure, applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of inability to provide electrostatic tolerance and easy burning
CN110620109AActive Publication Date: 2019-12-27ADVANCED ANALOG TECH INC
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
ADVANCED ANALOG TECH INC
Publication Date
2019-12-27

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Abstract

The invention discloses an electrostatic protection element layout structure with high electrostatic discharge tolerance. The structure comprises a plurality of NMOS transistors connected in parallel,wherein the NMOS transistors connected in parallel form an isolated NMOS multi-finger type semiconductor layout structure, a middle region of the isolated NMOS multi-finger semiconductor layout structure is a P-type doped region doped with high-energy P-type implanted ion concentration, so substrate resistance of the middle region is reduced. The structure is advantaged in that the total substrate resistance of the NMOS transistors corresponding to the middle region can be reduced, substrate resistance difference between the NMOS transistor corresponding to the middle region and the NMOS transistor corresponding to one of the NMOS transistors at two sides is reduced, so the NMOS transistors can be uniformly conducted, and the electrostatic discharge tolerance of the NMOS transistors is improved.
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Description

technical field

[0001] The present invention relates to an electrostatic protection element layout structure, in particular to an electrostatic protection element layout structure with high electrostatic discharge tolerance. Background technique

[0002] Generally speaking, in an integrated circuit (Integrated Circuit; IC) using a MOS process, the MOS element thereof is easily damaged by electrostatic high voltage discharge. Taking one of the ESD protection elements often used in an integrated circuit, that is, the NMOS transistor element 30 as an example, it includes a plurality of NMOS transistors connected in parallel, such as Figure 5A As shown, these NMOS transistors are formed on a P-type substrate 31; wherein the P-type substrate 31 is formed with an N-type isolation layer 32, a P-type doped region 33 and a P-type well 34 from bottom to top, and the The P-type well 34 is implanted with a plurality of drain doped regions 35 and a plurality of source doped regions 36, ...

Claims

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