37results about How to "Improve ESD tolerance" patented technology

A high-performance semiconductor apparatus which can be easily introduced into the MOS process, reduces the leakage current (electric field strength) between the emitter and the base, and is insusceptible to noise or surge voltage, and a manufacturing method of the semiconductor apparatus. The emitter 111 is formed by performing the ion implantation twice by using the conductive film (109) as a mask. The second emitter area (111b) is formed by ion implantation of a low impurity density impurity ion, and the first emitter area (111a) is formed by ion implantation of a high impurity density impurity ion. As a result, the low impurity density second emitter area is formed in the circumference of the emitter 111, which lowers the electric field strength, and reduces the leakage current. Also the conductive film is connected with the emitter electrode (116), which makes the apparatus insusceptible to noise.

A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor.

ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor light emitting element. The semiconductor light emitting element comprises a substrate, and a nitride buffer layer, an n-type layer, a shallow quantum well layer, a multiple quantum well layer and a p-type layer formed on the substrate sequentially. The semiconductor light emitting element is characterized in that a composite structure layer is also inserted between the shallow quantum well layer and the multiple quantum well layer; the composite structure layer at least comprises a p-type doped GaN layer, an n-type doped GaN layer, and an isolation layer located between the p-type doped GaN layer and the n-type doped GaN layer. The feature that p-type impurities in the composite structure layer are migrated to the shallow quantum well layer and the multiple quantum well layer is used, light emitting of the shallow quantum well layer and the composite structure layer is promoted while the light-emitting strength of the multiple quantum well layer is enhanced, the light outgoing area of the semiconductor element is increased, and the light-emitting strength is further enhanced.

An insulated gate semiconductor device includes a main insulated gate transistor having a gate electrode controlling a main current, a current-detecting insulated gate transistor, which is disposed in parallel to a main insulated gate transistor, outputting a current on a proportional basis in size between the transistors to the main current flowing through the main insulated gate transistor, a temperature detecting diode formed integrally with these insulated gate transistors in a semiconductor substrate. Interposing an ESD tolerance Zener diode between an emitter electrode of the current-detecting insulated gate transistor and an anode electrode of the temperature detecting diode leads to securing the ESD tolerance for the current-detecting insulated gate transistor by using the temperature detecting diode.

The embodiment of the invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a substrate, wherein the substrate comprises a first trap region, a second trap region positioned in a surface of the first trap region, a doped region positioned in a surface of the second trap region, field oxide positioned on the periphery of the doped region and a drift region positioned at the lower part of the field oxide, wherein a drain region is positioned in a surface of the doped region, and a certain distance is arranged between an edge of the drain region and an edge of the drift region. According to the invention, since the distance between the edge of the drain region and the edge of the drift region is changed and increased, the resistance between the edge of the drain region and the edge of the drift region is increased, a current flow path between the edge of the drain region and the edge of the drift region is increased, the maintaining voltage of the device is improved, therefore when an ESD (Electrostatic Discharge) phenomenon occurs, current between the drain region and the drift region is not concentrated, the caloric power of the device is reduced so as to avoid burn-out of the device, and the withstanding capability of the LDMOS device to ESD is improved.

A protective method and circuit distribution for electrostatic discharge of display device, which contains dividing a first input power line into plurality of second input power lines, setting an electrostatic protector around each second input power line for protecting from electrostatic discharge passing second power line, merging above mentioned second input power line into a third input power line.

According to one embodiment, a semiconductor element includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a control electrode, a pad unit, an insulating layer, and a conductor. The second semiconductor layer is provided on the first semiconductor layer. The first electrode is provided on the second semiconductor layer. The second electrode is provided on the second semiconductor layer. The control electrode is provided on the second semiconductor layer. The pad unit is provided on the second semiconductor layer. The pad unit is electrically connected to the control electrode. The insulating layer is provided on the second semiconductor layer. The insulating layer has an opening. The conductor is provided on the insulating layer. The conductor covers at least a part of the opening.

The invention discloses an electrostatic discharge protection circuit and a deep submicron semiconductor component thereof. A boundary between a heavily doped region corresponding to a drain electrodeof the deep submicron semiconductor component and an adjacent lightly doped region are pushed outwardly, so that a gap is formed between the boundary and the sidewall of the nearest grid insulating layer and the boundary is not aligned with the sidewall of the grid insulating layer. Thus, in the deep submicron semiconductor component, the drain electrode is not too close to a source electrode dueto smaller layout of a deep submicron technology, and the electrostatic discharge tolerance of the deep submicron semiconductor component is improved effectively.

Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via (16) is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.

A light-emitting diode device at least comprises a light-emitting diode chip and a packaging substrate used for bearing the light-emitting diode chip. The light-emitting diode chip comprises a semiconductor epitaxial layer, a first semiconductor epitaxial layer, a second semiconductor epitaxial layer and a light-emitting layer located between the semiconductor epitaxial layer and the second semiconductor epitaxial layer. Wherein a first metal layer and a second metal layer are oppositely arranged on the two surfaces of the substrate; the first metal layer and the second metal layer are opposite in polarity and form a capacitor with the insulating substrate, the first metal layer is electrically connected with the first semiconductor epitaxial layer, the second metal layer is electrically connected with the second semiconductor epitaxial layer, a parallel circuit is formed by the capacitor and the semiconductor epitaxial layers, and electrostatic protection is provided for the light-emitting diode by the aid of charging and discharging characteristics of the capacitor.