Electrostatic discharge protection circuit and deep submicron semiconductor component thereof

Abstract

The invention discloses an electrostatic discharge protection circuit and a deep submicron semiconductor component thereof. A boundary between a heavily doped region corresponding to a drain electrodeof the deep submicron semiconductor component and an adjacent lightly doped region are pushed outwardly, so that a gap is formed between the boundary and the sidewall of the nearest grid insulating layer and the boundary is not aligned with the sidewall of the grid insulating layer. Thus, in the deep submicron semiconductor component, the drain electrode is not too close to a source electrode dueto smaller layout of a deep submicron technology, and the electrostatic discharge tolerance of the deep submicron semiconductor component is improved effectively.

Description

Technical field [0001] The invention relates to a deep submicron semiconductor element, in particular to a deep submicron semiconductor element protected by electrostatic discharge. Background technique [0002] Since the internal components of integrated circuits are easily damaged by electrostatic discharge, electrostatic discharge protection engineering is particularly important for integrated circuits. See Image 6 As shown, since static electricity is easily discharged through the input / output pads 52 of the integrated circuit 50 to its internal components 51, an electrostatic discharge protection circuit 511 is provided on each input / output pad 52, which mainly includes a PMOS connected in series. (P-type metal-oxide-semiconductor element MP and an NMOS (N-type metal-oxide-semiconductor) element MN; wherein the series connection node of the PMOS element MP and the NMOS element MN is connected to the corresponding input / output pad 52, and The gate G and the source S of the P...

AI Technical Summary

Problems solved by technology

[0005] However, with the evolution of semiconductor technology, the components of integrated circuits have shrunk from micron to deep sub-micron (MOS gate width is less than 0.18um). Micron integrated circuit layout rules (VLSI layout rule) are relatively reduced, making the distance between the drain and source of the PMOS and NMOS components of the electrostatic discharge protection circuit too close, resulting in weakened antistatic capabilities; and because of the size of the PMOS and NMOS components Shrinking, electrostatic discharge current is easier to pass through the surface channels of PMOS and NMOS components, and burns PMOS and NMOS components

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