ESD protection component layout structure with high ESD tolerance

Abstract

The invention discloses a layout structure of an electrostatic protection element with high electrostatic discharge tolerance, which includes a plurality of parallel-connected NMOS transistors, and these parallel-connected NMOS transistors form an isolated NMOS multi-finger semiconductor layout structure; wherein the The middle region of the isolated NMOS multi-finger semiconductor layout structure is a P-type doped region doped with high-energy P-type implanted ion concentration, which reduces the substrate resistance of the middle region; thus, the corresponding The total substrate resistance of the NMOS transistor is reduced, and the substrate resistance difference between it and the NMOS transistor corresponding to one of the two sides is reduced, so that the NMOS transistor can be uniformly turned on, and the electrostatic discharge tolerance of the NMOS transistor is improved.

Description

technical field

[0001] The present invention relates to an electrostatic protection element layout structure, in particular to an electrostatic protection element layout structure with high electrostatic discharge tolerance. Background technique

[0002] Generally speaking, in an integrated circuit (Integrated Circuit; IC) using a MOS process, the MOS element thereof is easily damaged by electrostatic high voltage discharge. Taking one of the ESD protection elements often used in an integrated circuit, that is, the NMOS transistor element 30 as an example, it includes a plurality of NMOS transistors connected in parallel, such as Figure 5A As shown, these NMOS transistors are formed on a P-type substrate 31; wherein the P-type substrate 31 is formed with an N-type isolation layer 32, a P-type doped region 33 and a P-type well 34 from bottom to top, and the The P-type well 34 is implanted with a plurality of doped drain regions 35 and a plurality of doped source regions 36, ...

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