Transistor capable of boosting electro-static discharge tolerance and its layout method

Abstract

Transistors and their layout methods that can improve electrostatic discharge tolerance. The layout method includes: defining the first conductive type guard ring area; defining the first elongated second conductive type diffusion area; defining the second elongated second conductive type diffusion area, wherein the first and second elongated second conductive type diffusion areas The two conductive type diffusion areas are not connected; the ring type second conductivity type diffusion area is defined between the first and second elongated second conductivity type diffusion areas; the first conductivity type is defined inside the ring type second conductivity type diffusion area Diffusion area; a first grid is defined between the first elongated second conductivity type diffusion area and the ring type second conductivity type diffusion area; A second grid is defined between the conductive diffusion regions. The first and second elongated second conductive type diffusion regions are arranged parallel to each other inside the first conductive type guard ring region, and the first and second elongated second conductive type diffusion regions are arranged on the first conductive type on opposite sides of the type guard ring area.

Description

technical field [0001] The invention provides a transistor layout method, especially a transistor layout method that can improve electrostatic tolerance. Background technique [0002] As the dimensions of transistor components continue to shrink, the junction between the source and drain of transistors becomes shallower and the thickness of the gate oxide layer becomes thinner. When the thickness of the gate oxide layer becomes thinner and the breakdown voltage of the diode junction transistor decreases, the transistor is easily damaged by electrostatic discharge (ESD), so each pin of the base circuit chip needs to be protected by ESD protection components , and then connected to the internal wiring. [0003] see figure 1 , figure 1 It is a schematic diagram of an existing protective element 4 . One end of the protection element 4 is connected to a pad 2 and the other end is connected to a logic circuit 6 . When a large amount of electrostatic charge flows into the cont...

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Problems solved by technology

Please note that under this transistor layout, although the source and drain of the NMOS transistor 51 are far apart, the problem of the aforementioned NSCR transistor 10 can be solved, but the instantaneous large current input from the drain mainly flows through the P-type diffusion region 60 , if the area of ​​the P-type diffusion region 60 is too small, it may also cause damage to the NSCR transistor 50

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