Semiconductor device

Abstract

The invention provides a semiconductor device of ESD resistance while the width of the wiring pattern is not increased and the pin level of a chip of the semiconductor device is improved. A semiconductor device according to an embodiment includes a plurality of pads, a plurality of ESD protection circuits, each one of the ESD protection circuits being connected to a corresponding one of the plurality of pads, and an I / O circuit which is connected to a connection portion connecting output terminals of the plurality of ESD protection circuits to each other and which receives at least one input signal inputted into the plurality of pads.

Description

[0001] This application enjoys the priority of Japanese Patent Application No. 2012-198792 filed on September 10, 2012, and the entire content of the Japanese Patent Application is cited in this application. technical field [0002] Embodiments of the present invention relate to semiconductor devices. Background technique [0003] In electronic equipment, ESD countermeasures are taken to protect circuits from electrostatic destruction caused by electrostatic discharge (Electro-Static Discharge: hereinafter referred to as ESD). [0004] In order to evaluate ESD countermeasures, ESD resistance evaluations have been performed based on HBM (human body model) and MM (machine mode) according to the level of equipment or modules. For example, a voltage of 2KV to 3KV is applied under HBM and a voltage of 200V is applied under MM to a device or module to be evaluated, and ESD resistance evaluation is performed. [0005] In addition, for the level of electronic equipment or modules e...

AI Technical Summary

Problems solved by technology

[0007] However, the method of increasing the width of the wiring pattern not only imposes great constraints on the layout design of the chip, but also has the problem of increasing the area of ​​the chip and increasing the cost of the chip as a result.

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