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Integrated stacked ESD network in trench for trench DMOS

一种沟槽、多晶硅层的技术，应用在二极管、半导体器件、电气元件等方向，能够解决加增掩膜层工艺困难、复杂布置和金属布线等问题，达到良好ESD保护能力、简单金属布线的效果

Active Publication Date: 2020-01-10
蒙若贤
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In modern contact-on-trench processes, a layer of polysilicon on top of the silicon surface implies additional topology, which adds to the process difficulties of masking layers such as contact masks
Two stages of ESD diodes with resistors in between also require complex layout and metal routing

Method used

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  • Integrated stacked ESD network in trench for trench DMOS
  • Integrated stacked ESD network in trench for trench DMOS
  • Integrated stacked ESD network in trench for trench DMOS

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Embodiment Construction

[0032] The present invention will now be described more particularly, by way of example only, with reference to the accompanying drawings. It should be understood that the accompanying drawings are for better understanding and should not limit the present invention. Dimensions and features of components shown in the figures are generally chosen for convenience and clarity of presentation and are not necessarily shown to scale.

[0033] refer to figure 1 and figure 2 , the stacked ESD structure according to the first embodiment of the present invention includes a substrate 102 and an epitaxial layer 104 grown on the substrate 102 . The substrate 102 can be used as the drain of the trench DMOS, and the substrate is N-type or P-type semiconductor and heavily doped. The epitaxial layer 104 is the same semiconductor type as the substrate and is lightly doped. The thickness of the epitaxial layer 104 is generally 2-50 μm.

[0034] The stacked ESD structure further includes a t...

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Abstract

The embodiment of the invention discloses a stacked ESD structure that comprises a heavily doped substrate; an epitaxial layer grown on the substrate; a trench formed in the epitaxial layer; an oxidelayer formed on an inner sidewall of the trench; first and second poly layers formed in the trench; a plurality of P-type regions and N-type regions formed inside the first and second poly layers to make back to back diodes in the first and second poly layers respectively; a dielectric layer formed in the trench, between the first and second poly layers; an insulating layer formed on top of the second poly layer and the trench; a plurality of contact defined to connect the first poly layer, the poly resistor and the second poly layer, through the insulating layer; and a metal layer formed on top of the insulating layer.

Description

technical field [0001] The present invention relates to a trench double-diffused metal oxide semiconductor field effect transistor (hereinafter referred to as "trench DMOS"), and in particular to ESD (Electrostatic Discharge, electrostatic discharge) protection for trench DMOS. Background technique [0002] ESD is a common cause of failure of solid-state electronic components during the manufacturing process. High ESD voltages can cause damage to the gate oxide within the trench DMOS, resulting in transient or secondary failures. Component level ESD protection is essential to prevent this damage. [0003] One or several pairs of back-to-back PN diodes are usually used to divert high ESD charges before the voltage is high enough to damage the gate oxide. Due to the continuous advancement of technology, the die size of trench DMOS is shrinking, and the inherent ESD capability is also weakening. A single stage ESD diode is not sufficient, two stages of ESD diodes with a resi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0288H01L27/0255H01L27/0296H01L29/66674H01L29/7801
Inventor 蒙若贤黎茂林周德光
Owner 蒙若贤